From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932874AbcETCyx (ORCPT ); Thu, 19 May 2016 22:54:53 -0400 Received: from 216-12-86-13.cv.mvl.ntelos.net ([216.12.86.13]:58100 "EHLO brightrain.aerifal.cx" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755649AbcETCxK (ORCPT ); Thu, 19 May 2016 22:53:10 -0400 Message-Id: <2bdca4260d5bb2b3820e4309e2ba445c4c7bfbf6.1463708766.git.dalias@libc.org> In-Reply-To: References: From: Rich Felker Subject: [PATCH v2 03/12] of: add J-Core interrupt controller bindings To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sh@vger.kernel.org Cc: Ian Campbell , Jason Cooper , Kumar Gala , Marc Zyngier , Mark Rutland , Pawel Moll , Rob Herring , Thomas Gleixner Date: Fri, 20 May 2016 02:53:04 +0000 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Signed-off-by: Rich Felker --- .../bindings/interrupt-controller/jcore,aic.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt new file mode 100644 index 0000000..dc9fde8 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/jcore,aic.txt @@ -0,0 +1,28 @@ +J-Core Advanced Interrupt Controller + +Required properties: + +- compatible : Should be "jcore,aic1" for the (obsolete) first-generation aic + with 8 interrupt lines with programmable priorities, or "jcore,aic2" for + the "aic2" core with 64 interrupts. + +- interrupt-controller : Identifies the node as an interrupt controller + +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value shall be 1. + +Additional properties required for aic1: + +- reg : Memory region for configuration. + +- cpu-offset : For SMP, the offset to the per-cpu memory region for + configuration, to be scaled by the cpu number. + + +Example: + +aic: interrupt-controller { + compatible = "jcore,aic2"; + interrupt-controller; + #interrupt-cells = <1>; +}; -- 2.8.1