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[165.204.72.6]) by smtp.gmail.com with ESMTPSA id p13-20020adff20d000000b003176eab8868sm9459783wro.82.2023.09.11.01.38.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Sep 2023 01:38:31 -0700 (PDT) Message-ID: <2c097494-0854-3769-fb46-0f3fa59e06cb@gmail.com> Date: Mon, 11 Sep 2023 10:38:28 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.0 Subject: Re: [PATCH v2 1/2] drm/amd/display: fix the white screen issue when >= 64GB DRAM Content-Language: en-US To: Hamza Mahfooz , amd-gfx@lists.freedesktop.org Cc: Alan Liu , Lijo Lazar , dri-devel@lists.freedesktop.org, Mario Limonciello , David Airlie , Shashank Sharma , Rodrigo Siqueira , Aurabindo Pillai , Qingqing Zhuo , Harry Wentland , Stylon Wang , Victor Zhao , Srinivasan Shanmugam , Leo Li , Maarten Lankhorst , Le Ma , Hersen Wu , Yifan Zhang , Felix Kuehling , "Pan, Xinhui" , linux-kernel@vger.kernel.org, stable@vger.kernel.org, Hawking Zhang , Daniel Vetter , Wayne Lin , Alex Deucher , Candice Li , Lang Yu , =?UTF-8?Q?Christian_K=c3=b6nig?= , Luben Tuikov References: <20230908145521.39044-1-hamza.mahfooz@amd.com> From: =?UTF-8?Q?Christian_K=c3=b6nig?= In-Reply-To: <20230908145521.39044-1-hamza.mahfooz@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Am 08.09.23 um 16:55 schrieb Hamza Mahfooz: > From: Yifan Zhang > > Dropping bit 31:4 of page table base is wrong, it makes page table > base points to wrong address if phys addr is beyond 64GB; dropping > page_table_start/end bit 31:4 is unnecessary since dcn20_vmid_setup > will do that. Also, while we are at it, cleanup the assignments using > upper_32_bits()/lower_32_bits() and AMDGPU_GPU_PAGE_SHIFT. > > Cc: stable@vger.kernel.org > Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2354 > Fixes: 81d0bcf99009 ("drm/amdgpu: make display pinning more flexible (v2)") > Signed-off-by: Yifan Zhang > Signed-off-by: Hamza Mahfooz Reviewed-by: Christian König for the series as well. > --- > v2: use upper_32_bits()/lower_32_bits() and AMDGPU_GPU_PAGE_SHIFT > --- > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 +++++++++----- > 1 file changed, 9 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > index 1bb1a394f55f..5f14cd9391ca 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > @@ -1283,11 +1283,15 @@ static void mmhub_read_system_context(struct amdgpu_device *adev, struct dc_phy_ > > pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); > > - page_table_start.high_part = (u32)(adev->gmc.gart_start >> 44) & 0xF; > - page_table_start.low_part = (u32)(adev->gmc.gart_start >> 12); > - page_table_end.high_part = (u32)(adev->gmc.gart_end >> 44) & 0xF; > - page_table_end.low_part = (u32)(adev->gmc.gart_end >> 12); > - page_table_base.high_part = upper_32_bits(pt_base) & 0xF; > + page_table_start.high_part = upper_32_bits(adev->gmc.gart_start >> > + AMDGPU_GPU_PAGE_SHIFT); > + page_table_start.low_part = lower_32_bits(adev->gmc.gart_start >> > + AMDGPU_GPU_PAGE_SHIFT); > + page_table_end.high_part = upper_32_bits(adev->gmc.gart_end >> > + AMDGPU_GPU_PAGE_SHIFT); > + page_table_end.low_part = lower_32_bits(adev->gmc.gart_end >> > + AMDGPU_GPU_PAGE_SHIFT); > + page_table_base.high_part = upper_32_bits(pt_base); > page_table_base.low_part = lower_32_bits(pt_base); > > pa_config->system_aperture.start_addr = (uint64_t)logical_addr_low << 18;