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Thu, 07 Mar 2024 11:27:42 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 427BRgA3003248 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 7 Mar 2024 11:27:42 GMT Received: from [10.201.3.124] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 7 Mar 2024 03:27:36 -0800 Message-ID: <2c0e928e-e68c-e859-0e7f-c5a457f58175@quicinc.com> Date: Thu, 7 Mar 2024 16:57:32 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.9.1 Subject: Re: [PATCH v3 1/5] spi: dt-bindings: add binding doc for spi-qpic-snand Content-Language: en-US To: Krzysztof Kozlowski , , , , , , , , , , , , , , , CC: , References: <20240307041726.1648829-1-quic_mdalam@quicinc.com> <20240307041726.1648829-2-quic_mdalam@quicinc.com> <19d3c024-38aa-4526-b6c1-d9543b41fa2b@linaro.org> From: Md Sadre Alam In-Reply-To: <19d3c024-38aa-4526-b6c1-d9543b41fa2b@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ZUUeepn3sA288e4BF4c-IPv7pKV6tn9J X-Proofpoint-ORIG-GUID: ZUUeepn3sA288e4BF4c-IPv7pKV6tn9J X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-07_07,2024-03-06_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 suspectscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 phishscore=0 spamscore=0 mlxlogscore=999 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2402120000 definitions=main-2403070085 On 3/7/2024 1:16 PM, Krzysztof Kozlowski wrote: > On 07/03/2024 05:17, Md Sadre Alam wrote: > > There is no commit msg. Sorry missed it. Will add in next patch > > Subject did not improve. This is a friendly reminder during the review > process. Ok > > It seems my or other reviewer's previous comments were not fully > addressed. Maybe the feedback got lost between the quotes, maybe you > just forgot to apply it. Please go back to the previous discussion and > either implement all requested changes or keep discussing them. > > Thank you. Sorry, Will re-check all the previous comment and try to fix in next patch. > > >> Co-developed-by: Sricharan Ramabadhran >> Signed-off-by: Sricharan Ramabadhran >> Co-developed-by: Varadarajan Narayanan >> Signed-off-by: Varadarajan Narayanan >> Signed-off-by: Md Sadre Alam >> --- >> Change in [v3] >> >> * Updated commit message, removed "dt-bindings" from commit >> message >> >> * Updated compatible name as file name >> >> * Added hardware description >> >> * Documented clock-name >> >> * Moved dma-names property to top >> >> * Droped unused label "qpic_nand" >> >> * Fixed indentation in example dt node >> >> Change in [v2] >> >> * Added initial support for dt-bindings >> >> Change in [v1] >> >> * This patch was not included in [v1] >> >> .../bindings/spi/qcom,spi-qpic-snand.yaml | 83 +++++++++++++++++++ >> 1 file changed, 83 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml >> >> diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml >> new file mode 100644 >> index 000000000000..3d20a4bc567f >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml >> @@ -0,0 +1,83 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm QPIC NAND controller >> + >> +maintainers: >> + - Md sadre Alam >> + >> +description: | > > Do not need '|' unless you need to preserve formatting. Ok will do in next patch. > >> + The QCOM QPI-SPI-NAND flash controller is an extended version of >> + the QCOM QPIC NAND flash controller. It can work both in serial >> + and parallel mode. It supports typical SPI-NAND page cache >> + operations in single, dual or quad IO mode with pipelined ECC >> + encoding/decoding using the QPIC ECC HW engine. >> + >> +allOf: >> + - $ref: /schemas/spi/spi-controller.yaml# >> + >> +properties: >> + compatible: >> + enum: >> + - qcom,spi-qpic-snand >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + minItems: 3 > > Drop Ok will do in next patch. > >> + maxItems: 3 >> + >> + clock-names: >> + items: >> + - const: core >> + - const: aon >> + - const: iom > > Missing blank line Ok will do in next patch. > >> + dmas: >> + items: >> + - description: tx DMA channel >> + - description: rx DMA channel >> + - description: cmd DMA channel >> + >> + dma-names: >> + items: >> + - const: tx >> + - const: rx >> + - const: cmd >> + > > > Best regards, > Krzysztof >