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From: Jie Gan <jie.gan@oss.qualcomm.com>
To: James Clark <james.clark@linaro.org>, Jie Gan <jie.gan@oss.qualcomm.com>
Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Mike Leach <mike.leach@linaro.org>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Tingwei Zhang <tingwei.zhang@oss.qualcomm.com>
Subject: Re: [PATCH v1 1/3] coresight: tpda: Add sysfs node for tpda cross-trigger configuration
Date: Tue, 26 Aug 2025 17:24:40 +0800	[thread overview]
Message-ID: <2c542b10-ba75-4e75-a2cf-964edfbac52a@oss.qualcomm.com> (raw)
In-Reply-To: <ef2267d2-a6f4-4f51-be44-687a4074a4d3@linaro.org>



On 8/26/2025 5:17 PM, James Clark wrote:
> 
> 
> On 26/08/2025 8:01 am, Jie Gan wrote:
>> From: Tao Zhang <tao.zhang@oss.qualcomm.com>
>>
>> Introduce sysfs nodes to configure cross-trigger parameters for TPDA.
>> These registers define the characteristics of cross-trigger packets,
>> including generation frequency and flag values.
>>
>> Signed-off-by: Tao Zhang <tao.zhang@oss.qualcomm.com>
>> Co-developed-by: Jie Gan <jie.gan@oss.qualcomm.com>
>> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
>> ---
>>   .../testing/sysfs-bus-coresight-devices-tpda  |  43 ++++
>>   drivers/hwtracing/coresight/coresight-tpda.c  | 241 ++++++++++++++++++
>>   drivers/hwtracing/coresight/coresight-tpda.h  |  27 ++
>>   3 files changed, 311 insertions(+)
>>   create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight- 
>> devices-tpda
>>
> [...]
>> +#define TPDA_FPID_CR        (0x084)
>> +
>> +/* Cross trigger FREQ packets timestamp bit */
>> +#define TPDA_CR_FREQTS        BIT(2)
>> +/* Cross trigger FREQ packet request bit */
>> +#define TPDA_CR_FRIE        BIT(3)
>> +/* Cross trigger FLAG packet request interface bit */
>> +#define TPDA_CR_FLRIE        BIT(4)
>> +/* Cross trigger synchronization bit */
>> +#define TPDA_CR_SRIE        BIT(5)
>> +/* Packetize CMB/MCMB traffic bit */
>> +#define TPDA_CR_CMBCHANMODE    BIT(20)
>> +
>>   /* Aggregator port enable bit */
>>   #define TPDA_Pn_CR_ENA        BIT(0)
>>   /* Aggregator port CMB data set element size bit */
>>   #define TPDA_Pn_CR_CMBSIZE        GENMASK(7, 6)
>>   /* Aggregator port DSB data set element size bit */
>>   #define TPDA_Pn_CR_DSBSIZE        BIT(8)
>> +/* Mode control bit */
>> +#define TPDA_MODE_CTRL            BIT(12)
> 
> This one is missing the register name prefix, like TPDA_SYNCR_MODE_CTRL

Yes, you are right. Besides, I made a mistake here. I should put this 
Macro in patchset 2.

Anyway, I will fix it in next version.

Thanks,
Jie

> 
> 
> 
> 


  reply	other threads:[~2025-08-26  9:24 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-26  7:01 [PATCH v1 0/3] add sysfs nodes to configure TPDA's registers Jie Gan
2025-08-26  7:01 ` [PATCH v1 1/3] coresight: tpda: Add sysfs node for tpda cross-trigger configuration Jie Gan
2025-08-26  9:00   ` James Clark
2025-08-26  9:09     ` Jie Gan
2025-08-26  9:17       ` Jie Gan
2025-08-26  9:17   ` James Clark
2025-08-26  9:24     ` Jie Gan [this message]
2025-08-26  7:01 ` [PATCH v1 2/3] coresight: tpda: add function to configure TPDA_SYNCR register Jie Gan
2025-08-26  9:20   ` James Clark
2025-08-26  9:33     ` Jie Gan
2025-08-26  7:01 ` [PATCH v1 3/3] coresight: tpda: add sysfs node to flush specific port Jie Gan
2025-08-26  9:27   ` James Clark
2025-08-26  9:39     ` Jie Gan
2025-08-26  9:54       ` James Clark
2025-08-26 12:11         ` Jie Gan
2025-08-26 13:29           ` James Clark
2025-08-27  0:50             ` Jie Gan

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