From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753128AbdHKNEz (ORCPT ); Fri, 11 Aug 2017 09:04:55 -0400 Received: from mail-sn1nam02on0061.outbound.protection.outlook.com ([104.47.36.61]:54298 "EHLO NAM02-SN1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752763AbdHKNEw (ORCPT ); Fri, 11 Aug 2017 09:04:52 -0400 Subject: Re: [PATCH 1/2] devicetree: ARM: zynq: Add DT binding for eFuse controller To: Rob Herring , Michal Simek CC: , =?UTF-8?Q?S=c3=b6ren_Brinkmann?= , , , Steffen Trumtrar , , Peter Crosthwaite , Rob Herring , Mark Rutland , Josh Cartwright References: <4b4bfaad88f16d7229bf3da58be8f50f9d82a461.1501842586.git.michal.simek@xilinx.com> <20170810182547.7c6qtfikzekfq7pq@rob-hp-laptop> From: Michal Simek Message-ID: <2c5bc4a3-8213-976f-89d9-9050f100357a@xilinx.com> Date: Fri, 11 Aug 2017 15:04:42 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; 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11 Aug 2017 13:04:49.5964 (UTC) X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR02MB2246 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10.8.2017 20:25, Rob Herring wrote: > On Fri, Aug 04, 2017 at 12:29:53PM +0200, Michal Simek wrote: >> Add DT binding for eFuse controller available at Xilinx Zynq >> SoC. >> >> Signed-off-by: Michal Simek >> Acked-by: Sören Brinkmann >> --- >> >> Documentation/devicetree/bindings/arm/zynq/zynq-efuse.txt | 15 +++++++++++++++ > > Move to bindings/nvmem with the other efuse bindings. > > With that, > > Acked-by: Rob Herring done in v2. I have added your line. Please let me know if you see any problem. Thanks, Michal