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b=a2GaB9fwnBgLFPtjmp/3FkJnDSrXJErE8PXbA/mn+iFK3yJ7ilTk1PmKs/9QMieMy8eWUO+Y8RSvfE9YFYf53nNztEszwhgJx9gtZVXEvSsSa8oi3qRSsU4CP6d8B+CqRlaNqIRC4OCrlUuOyoGUOf7RkRk0XtKB7AkO7/RIdLc= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from CH1PR12MB9717.namprd12.prod.outlook.com (2603:10b6:610:2b2::8) by SA0PR12MB4464.namprd12.prod.outlook.com (2603:10b6:806:9f::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.202.18; Wed, 15 Jul 2026 13:09:01 +0000 Received: from CH1PR12MB9717.namprd12.prod.outlook.com ([fe80::b26:bd7c:5076:9cd4]) by CH1PR12MB9717.namprd12.prod.outlook.com ([fe80::b26:bd7c:5076:9cd4%6]) with mapi id 15.21.0202.014; Wed, 15 Jul 2026 13:09:00 +0000 Message-ID: <2c6bba39-58b7-47ed-879d-235ab23ef6ae@amd.com> Date: Wed, 15 Jul 2026 18:38:52 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] net: axienet: Clear stale AXI DMA TX/RX status before re-enabling interrupts To: Kusuma Vasana , radhey.shyam.pandey@amd.com, andrew+netdev@lunn.ch, davem@davemloft.net, dumazet@google.com, kuba@kernel.org, pabeni@redhat.com, michal.simek@amd.com, Suraj.Gupta2@amd.com Cc: git@amd.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260715125028.2104305-1-kusuma.vasana@amd.com> Content-Language: en-US From: "Pandey, Radhey Shyam" In-Reply-To: <20260715125028.2104305-1-kusuma.vasana@amd.com> Content-Type: text/plain; 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Completions arriving in this window cause hardware to latch > IOC/DELAY into the status register regardless of the control register > mask state. After NAPI completion, re-enabling interrupts immediately > re-asserts the IRQ line due to these stale status register bits, even > when no new work is pending. > > This results in a stale interrupt and redundant NAPI poll cycle with > no new work pending, causing unnecessary CPU processing. > > In the initial driver, the status register was cleared after polling > all packets, which naturally consumed any status accumulated during > processing. When the driver was converted to NAPI, status register > clearing was moved to the ISR before polling begins, leaving no > mechanism to clear status bits that arrive during the NAPI poll window. > Fix the same. rephrase - fix the same. Once addressed- feel free to add: Reviewed-by: Radhey Shyam Pandey Thanks! > > Signed-off-by: Kusuma Vasana > --- > drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c > index fcf517069d16..29050c8d04e2 100644 > --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c > +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c > @@ -1018,6 +1018,13 @@ static int axienet_tx_poll(struct napi_struct *napi, int budget) > netif_wake_queue(ndev); > } > > + /* Clear stale IOC/DELAY bits that may have latched during the > + * poll window to prevent a stale interrupt when there is no > + * work pending. > + */ > + axienet_dma_out32(lp, XAXIDMA_TX_SR_OFFSET, > + XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK); > + > if (packets < budget && napi_complete_done(napi, packets)) { > /* Re-enable TX completion interrupts. This should > * cause an immediate interrupt if any TX packets are > @@ -1293,6 +1300,13 @@ static int axienet_rx_poll(struct napi_struct *napi, int budget) > cur_p = &lp->rx_bd_v[lp->rx_bd_ci]; > } > > + /* Clear stale IOC/DELAY bits that may have latched during the > + * poll window to prevent a stale interrupt when there is no > + * work pending. > + */ > + axienet_dma_out32(lp, XAXIDMA_RX_SR_OFFSET, > + XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK); > + > u64_stats_update_begin(&lp->rx_stat_sync); > u64_stats_add(&lp->rx_packets, packets); > u64_stats_add(&lp->rx_bytes, size);