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Sat, 23 Nov 2024 18:00:15 +0100 (CET) Message-ID: <2c7fc07c-b431-4384-8dc6-3ae77b18367e@collabora.com> Date: Sat, 23 Nov 2024 19:00:14 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [v10,3/3] drm/rockchip: Add basic RK3588 HDMI output support To: Guenter Roeck Cc: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Sandy Huang , =?UTF-8?Q?Heiko_St=C3=BCbner?= , Andy Yan , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mark Yao , Sascha Hauer , Simona Vetter , Simona Vetter , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com, Alexandre ARNOUD , Luis de Arquer , Algea Cao References: <20241016-b4-rk3588-bridge-upstream-v10-3-87ef92a6d14e@collabora.com> <790091a1-00af-43bb-8cdf-814f4cc38d83@roeck-us.net> From: Cristian Ciocaltea Content-Language: en-US In-Reply-To: <790091a1-00af-43bb-8cdf-814f4cc38d83@roeck-us.net> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 11/23/24 5:56 PM, Guenter Roeck wrote: > On Wed, Oct 16, 2024 at 11:06:53PM +0300, Cristian Ciocaltea wrote: >> The RK3588 SoC family integrates the newer Synopsys DesignWare HDMI 2.1 >> Quad-Pixel (QP) TX controller IP and a HDMI/eDP TX Combo PHY based on a >> Samsung IP block. >> >> Add just the basic support for now, i.e. RGB output up to 4K@60Hz, >> without audio, CEC or any of the HDMI 2.1 specific features. >> >> Co-developed-by: Algea Cao >> Signed-off-by: Algea Cao >> Tested-by: Heiko Stuebner >> Reviewed-by: Maxime Ripard >> Signed-off-by: Cristian Ciocaltea >> --- > [ ... ] > >> +static void dw_hdmi_qp_rockchip_encoder_enable(struct drm_encoder *encoder) >> +{ >> + struct rockchip_hdmi_qp *hdmi = to_rockchip_hdmi_qp(encoder); >> + struct drm_crtc *crtc = encoder->crtc; >> + unsigned long long rate; >> + >> + /* Unconditionally switch to TMDS as FRL is not yet supported */ >> + gpiod_set_value(hdmi->enable_gpio, 1); >> + >> + if (crtc && crtc->state) { >> + rate = drm_hdmi_compute_mode_clock(&crtc->state->adjusted_mode, >> + 8, HDMI_COLORSPACE_RGB); >> + clk_set_rate(hdmi->ref_clk, rate); >> + /* >> + * FIXME: Temporary workaround to pass pixel clock rate >> + * to the PHY driver until phy_configure_opts_hdmi >> + * becomes available in the PHY API. See also the related >> + * comment in rk_hdptx_phy_power_on() from >> + * drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c >> + */ >> + phy_set_bus_width(hdmi->phy, rate / 100); > > On 32-bit systems: > > ERROR: modpost: "__udivdi3" [drivers/gpu/drm/rockchip/rockchipdrm.ko] undefined! > > in the mainline kernel. Yeah, that's a known issue and has been already fixed: https://lore.kernel.org/lkml/20241018151016.3496613-1-arnd@kernel.org/ Thanks, Cristian