From: "Suthikulpanit, Suravee" <suravee.suthikulpanit@amd.com>
To: Jason Gunthorpe <jgg@nvidia.com>
Cc: linux-kernel@vger.kernel.org, iommu@lists.linux.dev,
joro@8bytes.org, robin.murphy@arm.com, vasant.hegde@amd.com,
kevin.tian@intel.com, jon.grimm@amd.com, santosh.shukla@amd.com,
pandoh@google.com, kumaranand@google.com
Subject: Re: [PATCH v5 3/6] iommu/amd: Modify set_dte_entry() to use 256-bit DTE helpers
Date: Wed, 16 Oct 2024 12:12:28 +0700 [thread overview]
Message-ID: <2cca938f-9229-435a-a038-c431fcff0622@amd.com> (raw)
In-Reply-To: <20241007140502.GO1365916@nvidia.com>
On 10/7/2024 9:05 PM, Jason Gunthorpe wrote:
> On Mon, Oct 07, 2024 at 04:13:50AM +0000, Suravee Suthikulpanit wrote:
>> +static void make_clear_dte(struct amd_iommu *iommu, struct dev_table_entry *dte,
>> + struct dev_table_entry *new)
>> +{
>> + new->data[0] = DTE_FLAG_V;
>> +
>> + /* Apply erratum 63 */
>> + if (FIELD_GET(DTE_SYSMGT_MASK, dte->data[1]) == 0x01)
>> + new->data[0] |= BIT_ULL(DEV_ENTRY_IW);
>> +
>> + if (!amd_iommu_snp_en)
>> + new->data[0] |= DTE_FLAG_TV;
>
> It would be nice to have a comment here..
I am moving this check. See description below...
> clear_dte() must create a blocking configuration as several callers
> depend on that.
Right, I missed that. I'll rework this function.
> Why is blocking with TV=1,Mode=0,IW=0,IR=0 used sometimes but
> sometimes TV=0 is used instead?
Originally, when DTE[Mode]=0, the TV bit is set.
Then, the commit b9f0043e1ea6 "iommu/amd: Set translation valid bit only
when IO page tables are in use" clears the TV ONLY when running on
SNP-enabled system. We didn't clear the bit for all cases since there
was a concern whether it would cause regression on older platforms.
However, I am considering clearing the TV flag for all cases to simplify
the logic since it should not violate the spec.
>> + /* Need to preserve interrupt remapping information in DTE[128:255] */
>> + new->data128[1] = dte->data128[1];
>
> It doesn't need to preserve.. write_dte_upper128() does the
> preservation automatically under the right lock. Any bits in
> DTE_DATA2_INTR_MASK should be 0 for the input DTE because they will be
> ignored by the masking:
>
> + new->data[2] &= ~DTE_DATA2_INTR_MASK;
> + new->data[2] |= old.data[2] & (DTE_DATA2_INTR_MASK | DTE_DATA2_RESV_MASK);
>
> Also this shouldn't preserve the top Guest related 64 bit for a 'clear
> dte' either.
>
> So, I think this can just be
>
> new->data128[1] = 0;
>
> ?
Good point. I'll clean this up.
Thanks,
Suravee
next prev parent reply other threads:[~2024-10-16 5:12 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-07 4:13 [PATCH v5 0/6] iommu/amd: Use 128-bit cmpxchg operation to update DTE Suravee Suthikulpanit
2024-10-07 4:13 ` [PATCH v5 1/6] iommu/amd: Disable AMD IOMMU if CMPXCHG16B feature is not supported Suravee Suthikulpanit
2024-10-07 4:13 ` [PATCH v5 2/6] iommu/amd: Introduce helper function to update 256-bit DTE Suravee Suthikulpanit
2024-10-07 14:06 ` Jason Gunthorpe
2024-10-11 5:25 ` Suthikulpanit, Suravee
2024-10-07 14:42 ` Uros Bizjak
2024-10-11 10:22 ` Suthikulpanit, Suravee
2024-10-11 11:05 ` Uros Bizjak
2024-10-07 4:13 ` [PATCH v5 3/6] iommu/amd: Modify set_dte_entry() to use 256-bit DTE helpers Suravee Suthikulpanit
2024-10-07 14:05 ` Jason Gunthorpe
2024-10-16 5:12 ` Suthikulpanit, Suravee [this message]
2024-10-07 14:17 ` Jason Gunthorpe
2024-10-16 5:15 ` Suthikulpanit, Suravee
2024-10-07 4:13 ` [PATCH v5 4/6] iommu/amd: Introduce helper function get_dte256() Suravee Suthikulpanit
2024-10-07 4:13 ` [PATCH v5 5/6] iommu/amd: Modify clear_dte_entry() to avoid in-place update Suravee Suthikulpanit
2024-10-07 14:10 ` Jason Gunthorpe
2024-10-07 4:13 ` [PATCH v5 6/6] iommu/amd: Lock DTE before updating the entry with WRITE_ONCE() Suravee Suthikulpanit
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