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Fri, 1 May 2020 14:16:37 +0000 Subject: Re: [PATCH v4 1/6] arch/x86/kvm: Refactor l1d flush lifecycle management To: "Singh, Balbir" , "tglx@linutronix.de" , "linux-kernel@vger.kernel.org" Cc: "keescook@chromium.org" , "tony.luck@intel.com" , "benh@kernel.crashing.org" , "jpoimboe@redhat.com" , "x86@kernel.org" , "dave.hansen@intel.com" References: <20200423140125.7332-1-sblbir@amazon.com> <20200423140125.7332-2-sblbir@amazon.com> From: Tom Lendacky Message-ID: <2cf3ae4b-b623-1489-0700-20ac3c24d5a1@amd.com> Date: Fri, 1 May 2020 09:16:35 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-ClientProxiedBy: SN4PR0201CA0012.namprd02.prod.outlook.com (2603:10b6:803:2b::22) To DM5PR12MB1355.namprd12.prod.outlook.com (2603:10b6:3:6e::7) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from office-linux.texastahm.com (67.79.209.213) by SN4PR0201CA0012.namprd02.prod.outlook.com (2603:10b6:803:2b::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2958.20 via Frontend Transport; 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Is this value based on a 32KB data >>> cache and the idea is to write twice the size of the cache to be sure that >>> every entry has been replaced - with the second 32KB to catch the odd line >>> that might not have been pulled in? >>> >> >> Currently the only users are VMX L1TF and optional prctl(). It should be >> based >> on actual L1D cache size, I checked a little bit and the largest L1D cache >> size across various x86 bits is 64K. so there are three options here: >> >> 1. We refactor the code, we would need to save the L1D cache size and use >> cpu_dev callbacks for L1D flush >> 2. We can make the current code depend on L1D_FLUSH MSR and enable it only >> when that feature is available. There would be no software fallback. Then >> follow it up with #1 >> 3. We keep the code as is on the assumption that all of L1D <= 64K across >> the >> current platforms and we do #1 in a followup (since the prctl is optional >> and >> the only other user is the VMX code). >> >> Thanks for the review, >> Balbir Singh. >> > > Tom, > > I have the following changes that I think will suffice for now (these are not > properly formatted, but you get the idea) > > diff --git a/arch/x86/kernel/l1d_flush.c b/arch/x86/kernel/l1d_flush.c > index a754b6c288a9..7fec0cc8f85c 100644 > --- a/arch/x86/kernel/l1d_flush.c > +++ b/arch/x86/kernel/l1d_flush.c > @@ -92,6 +92,9 @@ int l1d_flush_init_once(void) > { > int ret = 0; > > + if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) > + return -ENOTSUPP; > + > if (static_cpu_has(X86_FEATURE_FLUSH_L1D) || l1d_flush_pages) > return ret; > > > Does that satisfy your comments about patch 1/6 and 2/6 in the series? Yes, that works. Thanks, Tom > > Balbir Singh. >