From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751982AbdJROK7 (ORCPT ); Wed, 18 Oct 2017 10:10:59 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:8547 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751519AbdJROKz (ORCPT ); Wed, 18 Oct 2017 10:10:55 -0400 Subject: Re: [PATCH v5 3/6] perf: hisi: Add support for HiSilicon SoC L3C PMU driver To: Mark Rutland References: <1503389277-134131-1-git-send-email-zhangshaokun@hisilicon.com> <1503389277-134131-4-git-send-email-zhangshaokun@hisilicon.com> <20171017151657.fr4k63bynmc65woo@lakrids.cambridge.arm.com> <04e32a88-a719-9a4a-1f07-fb452e227297@hisilicon.com> <20171018135530.qo54qe36zplp4etp@lakrids.cambridge.arm.com> CC: , , , , , , Anurup M From: Zhangshaokun Message-ID: <2cf90805-e176-fe6f-2c37-59ce71c51781@hisilicon.com> Date: Wed, 18 Oct 2017 22:08:15 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 MIME-Version: 1.0 In-Reply-To: <20171018135530.qo54qe36zplp4etp@lakrids.cambridge.arm.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.74.221.148] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020204.59E760D7.0261,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 192c01e3ce635f4dfd62609a97fe0378 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Mark, Thanks for your further explanation. On 2017/10/18 21:55, Mark Rutland wrote: > On Wed, Oct 18, 2017 at 09:33:30PM +0800, Zhangshaokun wrote: >> On 2017/10/17 23:16, Mark Rutland wrote: >>> On Tue, Aug 22, 2017 at 04:07:54PM +0800, Shaokun Zhang wrote: >>>> +static int hisi_l3c_pmu_init_data(struct platform_device *pdev, >>>> + struct hisi_pmu *l3c_pmu) >>>> +{ >>>> + unsigned long long id; >>>> + struct resource *res; >>>> + acpi_status status; >>>> + int cpu; >>>> + >>>> + status = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev), >>>> + "_UID", NULL, &id); >>>> + if (ACPI_FAILURE(status)) >>>> + return -EINVAL; >>>> + >>>> + l3c_pmu->id = id; >>>> + >>>> + /* >>>> + * Use the SCCL_ID and CCL_ID to identify the L3C PMU, while >>>> + * SCCL_ID is in MPIDR[aff2] and CCL_ID is in MPIDR[aff1]. >>>> + */ >>>> + if (device_property_read_u32(&pdev->dev, "hisilicon,scl-id", >>>> + &l3c_pmu->sccl_id)) { >>>> + dev_err(&pdev->dev, "Can not read l3c sccl-id!\n"); >>>> + return -EINVAL; >>>> + } >>>> + >>>> + if (device_property_read_u32(&pdev->dev, "hisilicon,ccl-id", >>>> + &l3c_pmu->ccl_id)) { >>>> + dev_err(&pdev->dev, "Can not read l3c ccl-id!\n"); >>>> + return -EINVAL; >>>> + } >>>> + >>>> + /* Initialise the associated cpumask of the PMU */ >>>> + for_each_present_cpu(cpu) >>>> + smp_call_function_single(cpu, hisi_l3c_pmu_set_cpumask_by_ccl, >>>> + (void *)l3c_pmu, 1); > >>> Rather than a proble-time smp_call_function_single(), can you follow the >>> qcom l2's approach of associating CPUs with a PMU instance in the >>> notifier? That will work even if CPUs are brought online very late. >> >> A good guidance, but HHA and DDRC PMUs are different from L3C PMU, the former >> share the same SCCL and the latter share the same SCCL and CCL. I will >> try to deal with this difference in online notifier. > > FWIW, I think it makes sense for each PMU to have its own notifier > (perhaps with some shared code that each calls to do the migration). > > I just want to avoid the smp_call_function_single() at probe time, as > that doesn't work in some cases. > Got it, i shall update the hisi_pmu::associated_cpus only in online and offline notifiers. Thanks, Shaokun > Thanks, > Mark. > > . >