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Tue, 2 Feb 2021 17:45:23 +0000 From: "Bedel, Alban" To: "bgolaszewski@baylibre.com" CC: "linux-gpio@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linus.walleij@linaro.org" Subject: Re: [PATCH] gpio: pca953x: add support for open drain pins on PCAL6524 Thread-Topic: [PATCH] gpio: pca953x: add support for open drain pins on PCAL6524 Thread-Index: AQHW9YtTve2FLqoyiEecHFkdtDbNF6pExeaAgABlRAA= Date: Tue, 2 Feb 2021 17:45:23 +0000 Message-ID: <2d0ef621261d40a4ce8e39d0103c0db49f087a49.camel@aerq.com> References: <20210128153601.153126-1-alban.bedel@aerq.com> In-Reply-To: Accept-Language: en-DE, de-DE, en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: Authentication-Results-Original: baylibre.com; dkim=none (message not signed) header.d=none;baylibre.com; dmarc=none action=none header.from=aerq.com; x-originating-ip: [88.130.51.118] x-ms-publictraffictype: Email X-MS-Office365-Filtering-Correlation-Id: ea6a1f86-1df2-499b-9f4d-08d8c7a252e3 x-ms-traffictypediagnostic: DB9PR10MB4618:|AM6PR10MB2312: X-Microsoft-Antispam-PRVS: x-ms-oob-tlc-oobclassifiers: OLM:9508;OLM:8882; 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X-OriginatorOrg: aerq.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2021 17:45:25.7115 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ea6a1f86-1df2-499b-9f4d-08d8c7a252e3 X-MS-Exchange-CrossTenant-Id: bf24ff3e-ad0a-4c79-a44a-df7092489e22 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=bf24ff3e-ad0a-4c79-a44a-df7092489e22;Ip=[52.169.0.179];Helo=[eu2.smtp.exclaimer.net] X-MS-Exchange-CrossTenant-AuthSource: AM5EUR03FT035.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR10MB2312 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --=-P9BNSaSpMKOFAPnoHxih Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, 2021-02-02 at 12:42 +0100, Bartosz Golaszewski wrote: > On Thu, Jan 28, 2021 at 4:36 PM Alban Bedel > wrote: > > From a quick glance at various datasheet the PCAL6524 seems to be > > the > > only chip in this familly that support setting the drive mode of > > single pins. Other chips either don't support it at all, or can > > only > > set the drive mode of whole banks, which doesn't map to the GPIO > > API. > >=20 > > Add a new flag, PCAL6524, to mark chips that have the extra > > registers > > needed for this feature. Then mark the needed register banks as > > readable and writable, here we don't set OUT_CONF as writable, > > although it is, as we only need to read it. Finally add a function > > that configure the OUT_INDCONF register when the GPIO API set the > > drive mode of the pins. > >=20 > > Signed-off-by: Alban Bedel > > --- > > drivers/gpio/gpio-pca953x.c | 64 > > +++++++++++++++++++++++++++++++++++-- > > 1 file changed, 61 insertions(+), 3 deletions(-) > >=20 > > diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio- > > pca953x.c > > index 825b362eb4b7..db0b3dab1490 100644 > > --- a/drivers/gpio/gpio-pca953x.c > > +++ b/drivers/gpio/gpio-pca953x.c > > @@ -64,6 +64,8 @@ > > #define PCA_INT BIT(8) > > #define PCA_PCAL BIT(9) > > #define PCA_LATCH_INT (PCA_PCAL | PCA_INT) > > +#define PCAL6524 BIT(10) >=20 > Maybe call it PCAL6524_TYPE for consistency with the ones below? This is a flag that, like the above ones, indicate the existence of registers, the types found under indicate a different register layout. Misusing the naming convention would probably be confusing. A generic name that don't reference the part type (PCA_???) would perhaps be better but as I couldn't find any other part with these registers I left it at that for now. > > + >=20 > No need for this newline. I'll fix all the style issues you pointed out. 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