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Wed, 26 Feb 2025 07:07:13 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51Q77CLa015990 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 26 Feb 2025 07:07:12 GMT Received: from [10.64.68.153] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 25 Feb 2025 23:07:07 -0800 Message-ID: <2d16609b-2423-489e-a45c-0e73ee9af006@quicinc.com> Date: Wed, 26 Feb 2025 15:07:05 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v14 05/10] Coresight: Allocate trace ID after building the path From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" , Maxime Coquelin , Alexandre Torgue , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio CC: Tingwei Zhang , Jinlong Mao , , , , , , References: <20250226041342.53933-1-quic_jiegan@quicinc.com> <20250226041342.53933-6-quic_jiegan@quicinc.com> Content-Language: en-US In-Reply-To: <20250226041342.53933-6-quic_jiegan@quicinc.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: sE1QsX_3kYUv6bDqm3J0z-mkWUDmhznT X-Proofpoint-ORIG-GUID: sE1QsX_3kYUv6bDqm3J0z-mkWUDmhznT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-25_08,2025-02-26_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 clxscore=1015 malwarescore=0 impostorscore=0 adultscore=0 priorityscore=1501 spamscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2502260055 On 2/26/2025 12:13 PM, Jie Gan wrote: > The trace_id will be stored in coresight_path instead of being declared > everywhere and allocated after building the path. > > Signed-off-by: Jie Gan Correct tags: Co-developed-by: James Clark Signed-off-by: James Clark Signed-off-by: Jie Gan Jie > --- > drivers/hwtracing/coresight/coresight-core.c | 44 +++++++++++++++++++ > .../hwtracing/coresight/coresight-etm-perf.c | 5 +-- > drivers/hwtracing/coresight/coresight-priv.h | 2 + > drivers/hwtracing/coresight/coresight-sysfs.c | 4 ++ > 4 files changed, 52 insertions(+), 3 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c > index 9c2a088a28d8..7d010d996f01 100644 > --- a/drivers/hwtracing/coresight/coresight-core.c > +++ b/drivers/hwtracing/coresight/coresight-core.c > @@ -654,6 +654,50 @@ static void coresight_drop_device(struct coresight_device *csdev) > } > } > > +/* > + * coresight device will read their existing or alloc a trace ID, if their trace_id > + * callback is set. > + * > + * Return 0 if the trace_id callback is not set. > + * Return the result of the trace_id callback if it is set. The return value > + * will be the trace_id if successful, and an error number if it fails. > + */ > +static int coresight_get_trace_id(struct coresight_device *csdev, > + enum cs_mode mode, > + struct coresight_device *sink) > +{ > + if (coresight_ops(csdev)->trace_id) > + return coresight_ops(csdev)->trace_id(csdev, mode, sink); > + > + return 0; > +} > + > +/* > + * Call this after creating the path and before enabling it. This leaves > + * the trace ID set on the path, or it remains 0 if it couldn't be assigned. > + */ > +void coresight_path_assign_trace_id(struct coresight_path *path, > + enum cs_mode mode) > +{ > + struct coresight_device *sink = coresight_get_sink(&path->path_list); > + struct coresight_node *nd; > + int trace_id; > + > + list_for_each_entry(nd, &path->path_list, link) { > + /* Assign a trace ID to the path for the first device that wants to do it */ > + trace_id = coresight_get_trace_id(nd->csdev, mode, sink); > + > + /* > + * 0 in this context is that it didn't want to assign so keep searching. > + * Non 0 is either success or fail. > + */ > + if (trace_id != 0) { > + path->trace_id = trace_id; > + return; > + } > + } > +} > + > /** > * _coresight_build_path - recursively build a path from a @csdev to a sink. > * @csdev: The device to start from. > diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c > index b0426792f08a..134290ab622e 100644 > --- a/drivers/hwtracing/coresight/coresight-etm-perf.c > +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c > @@ -319,7 +319,6 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, > { > u32 id, cfg_hash; > int cpu = event->cpu; > - int trace_id; > cpumask_t *mask; > struct coresight_device *sink = NULL; > struct coresight_device *user_sink = NULL, *last_sink = NULL; > @@ -409,8 +408,8 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, > } > > /* ensure we can allocate a trace ID for this CPU */ > - trace_id = coresight_trace_id_get_cpu_id_map(cpu, &sink->perf_sink_id_map); > - if (!IS_VALID_CS_TRACE_ID(trace_id)) { > + coresight_path_assign_trace_id(path, CS_MODE_PERF); > + if (!IS_VALID_CS_TRACE_ID(path->trace_id)) { > cpumask_clear_cpu(cpu, mask); > coresight_release_path(path); > continue; > diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h > index 27b7dc348d4a..2bea35bae0d4 100644 > --- a/drivers/hwtracing/coresight/coresight-priv.h > +++ b/drivers/hwtracing/coresight/coresight-priv.h > @@ -152,6 +152,8 @@ int coresight_make_links(struct coresight_device *orig, > void coresight_remove_links(struct coresight_device *orig, > struct coresight_connection *conn); > u32 coresight_get_sink_id(struct coresight_device *csdev); > +void coresight_path_assign_trace_id(struct coresight_path *path, > + enum cs_mode mode); > > #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X) > extern int etm_readl_cp14(u32 off, unsigned int *val); > diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/hwtracing/coresight/coresight-sysfs.c > index cb4c39732d26..d03751bf3d8a 100644 > --- a/drivers/hwtracing/coresight/coresight-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-sysfs.c > @@ -209,6 +209,10 @@ int coresight_enable_sysfs(struct coresight_device *csdev) > goto out; > } > > + coresight_path_assign_trace_id(path, CS_MODE_SYSFS); > + if (!IS_VALID_CS_TRACE_ID(path->trace_id)) > + goto err_path; > + > ret = coresight_enable_path(&path->path_list, CS_MODE_SYSFS, NULL); > if (ret) > goto err_path;