From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD8243A5E78 for ; Thu, 23 Jul 2026 05:47:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784785677; cv=none; b=AWil3oyaxy3zeJHUFudacldlYkYXdaGtBwjzI/GxISSOUjduevfBpdzVvo87AmSKp5J6dD8lyLOIvPhB4gVPYMHg8p8u3xTPV4Md1sYw4dsTJYdBuYPcXBZ8Y/7Tj7u9KVYQixcbo0JEQcNhydYGNZzkolqBKOaj6tTgsFsy5d0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784785677; c=relaxed/simple; bh=UEUylPmzFnBo4UVGO9yk/CSuZKNdrB5NwZXwXC5qvL8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CMABsNz3QvE/BVNoj5wsCLXhRcTDmC5Chi0Qsa8/N2lELd3bhFUUunYr/CIm6RwKOA0PTZjaL8kc3CHIx/0zytpUpwi5upQp3Gu3kZFm6clt3PMOebD9cGJVuo0FeZW4kDXf97B5MSM325qHE6BdcLCpJ0CIH6e+pH6/2P3stkA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=la3pESIv; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="la3pESIv" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7AC8C1F000E9; Thu, 23 Jul 2026 05:47:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784785675; bh=fVLDlt7OtdkiHRmNBt6TGjSGEaADwUAmP2pyF+NsbLs=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=la3pESIvb0vKthAkinN9/m4VDQBwYEkfEgyPczpORfHNHuBtdl1ZQEs2ELKe64zJZ YpufYj6oAMaCTL9oYPWJZ5U3fpiJOMKtid4nBAWTiWyr5usLPmoe6R2D3+9ygCZa1b zRHra8kqXFTDKdny6UszUBczwbZjvD64ekYewMe6shMOOi6+hlLNm9yTqERgHjbHOL VMg5WjkLwRJAjn31Cpm+it2aOxlaAOyEsu/VayF8oyrPIaVl/qJXixLyBRMnzgscG0 b8eZ75mPgWYcjrGCfaVT8kcEwSQ6fkIrMhuQtedsJCpyw1m/QmMZZwq4CPP+bequPl 4E4mMmBffYXEg== From: "Naveen N Rao (AMD)" To: Borislav Petkov , Dave Hansen Cc: , , Thomas Gleixner , Nikunj A Dadhania , Manali Shukla , Bharata B Rao , "H. Peter Anvin" Subject: [PATCH v4 1/3] perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10 Date: Thu, 23 Jul 2026 11:14:06 +0530 Message-ID: <2d18caf834a2e66e4c6787e3c3058fd6bb6e5d3e.1784785046.git.naveen@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit For AMD family 0x10, EILVT offsets are not assigned by BIOS and is instead assigned by picking the next available EILVT offset. Use the maximum EILVT count for family 0x10 (APIC_EILVT_NR_AMD_10H) rather than an arbitrary maximum EILVT count when looking for the next available EILVT offset. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- arch/x86/events/amd/ibs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 3531f9c23b8c..555912ac520f 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -1839,13 +1839,13 @@ static void force_ibs_eilvt_setup(void) preempt_disable(); /* find the next free available EILVT entry, skip offset 0 */ - for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) { + for (offset = 1; offset < APIC_EILVT_NR_AMD_10H; offset++) { if (get_eilvt(offset)) break; } preempt_enable(); - if (offset == APIC_EILVT_NR_MAX) { + if (offset == APIC_EILVT_NR_AMD_10H) { pr_debug("No EILVT entry available\n"); return; } -- 2.54.0