Re: [PATCH v3 1/2] arm64: dts: socfpga: agilex5: Enable the SMMU

[Krzysztof Kozlowski <krzk@kernel.org>]

On 04/06/2026 12:50, muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
> From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
> 
> The SMMU is disabled in socfpga_agilex5.dtsi. The SoC uses a different
> memory-mapped base address for its peripherals, which requires the SMMU
> to be active so that the Secure Device Manager (SDM) can correctly
> access those regions through address translation.
> 
> Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
> ---
> Changes in v3:
> - Fix commit header to follow subsystem naming convention
> - Remove commit body line that restated the subject
> - Clarify which file had the SMMU disabled
> 
> Changes in v2:
> - Move SMMU enable into the base DTSI file instead of individual DTS files
> ---
>  arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index b06c6d5d60ee..64f3739a0c33 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -385,7 +385,7 @@ smmu: iommu@16000000 {
>  			interrupt-names = "eventq", "gerror", "priq";
>  			dma-coherent;
>  			#iommu-cells = <1>;
> -			status = "disabled";
> +			status = "okay";

NAK. Nothing improved and you gave me exactly MINUS 5 minutes to reply
to your comment. You FIRST sent v3 and then 5 minutes later you replied
to my comment. So I should go back in time? How do you imagine this
process working?

Best regards,
Krzysztof