From: Philipp Zabel <p.zabel@pengutronix.de>
To: Changhuang Liang <changhuang.liang@starfivetech.com>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Stephen Boyd <sboyd@kernel.org>, Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Emil Renner Berthing <kernel@esmil.dk>,
Kees Cook <kees@kernel.org>,
"Gustavo A . R . Silva" <gustavoars@kernel.org>,
Richard Cochran <richardcochran@gmail.com>
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-hardening@vger.kernel.org, netdev@vger.kernel.org,
Sia Jee Heng <jeeheng.sia@starfivetech.com>,
Hal Feng <hal.feng@starfivetech.com>,
Ley Foon Tan <leyfoon.tan@starfivetech.com>
Subject: Re: [PATCH v1 05/22] dt-bindings: clock: Add StarFive JHB100 System-0 clock and reset generator
Date: Thu, 02 Apr 2026 14:22:29 +0200 [thread overview]
Message-ID: <2d3ef7359f63fb364cb7bc13b721132894428874.camel@pengutronix.de> (raw)
In-Reply-To: <20260402105523.447523-6-changhuang.liang@starfivetech.com>
On Do, 2026-04-02 at 03:55 -0700, Changhuang Liang wrote:
> Add bindings for the System-0 clocks and reset generator (SYS0CRG) on
> JHB100 SoC.
>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> ---
> .../clock/starfive,jhb100-sys0crg.yaml | 63 +++++++++++++++++++
> .../dt-bindings/clock/starfive,jhb100-crg.h | 56 +++++++++++++++++
> .../dt-bindings/reset/starfive,jhb100-crg.h | 30 +++++++++
> 3 files changed, 149 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-sys0crg.yaml
> create mode 100644 include/dt-bindings/clock/starfive,jhb100-crg.h
> create mode 100644 include/dt-bindings/reset/starfive,jhb100-crg.h
>
[...]
> diff --git a/include/dt-bindings/reset/starfive,jhb100-crg.h b/include/dt-bindings/reset/starfive,jhb100-crg.h
> new file mode 100644
> index 000000000000..71affdcdf733
> --- /dev/null
> +++ b/include/dt-bindings/reset/starfive,jhb100-crg.h
> @@ -0,0 +1,30 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR MIT */
> +/*
> + * Copyright (C) 2024 StarFive Technology Co., Ltd.
> + * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
> + *
> + */
> +
> +#ifndef __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__
> +#define __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__
> +
> +/* SYS0CRG resets */
> +#define JHB100_SYS0RST_RESOURCE_ARB 0
Where are resets 1 and 2, ...
> +#define JHB100_SYS0RST_SYS0_IOMUX_PRESETN 3
> +#define JHB100_SYS0RST_SYS0H_IOMUX_PRESETN 4
> +#define JHB100_SYS0RST_RST_ADAPTOR_TIMEOUT_RSTN 5
... where are 6-13?
> +
> +#define JHB100_SYS0RST_BMCPCIERP_RSTN_BUS 14
[...]
If there are non-reset bits in these registers, please enumerate reset
controls in a contiguous range for this binding and add a mapping table
in the driver.
regards
Philipp
next prev parent reply other threads:[~2026-04-02 12:22 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-02 10:55 [PATCH v1 00/22] Add basic clocks and resets for JHB100 SoC Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 01/22] reset: starfive: Rename file name "jh71x0" to "common" Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 02/22] reset: starfive: Convert the word "jh71x0" to "starfive" Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 03/22] clk: starfive: Rename file name "jh71x0" to "common" Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 04/22] clk: starfive: Convert the word "jh71x0" to "starfive" Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 05/22] dt-bindings: clock: Add StarFive JHB100 System-0 clock and reset generator Changhuang Liang
2026-04-02 12:22 ` Philipp Zabel [this message]
2026-04-03 0:53 ` Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 06/22] clk: starfive: Add JHB100 System-0 clock generator driver Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 07/22] dt-bindings: clock: Add StarFive JHB100 System-1 clock and reset generator Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 08/22] clk: starfive: Add JHB100 System-1 clock generator driver Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 09/22] dt-bindings: clock: Add StarFive JHB100 System-2 clock and reset generator Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 10/22] clk: starfive: Add JHB100 System-2 clock generator driver Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 11/22] dt-bindings: clock: Add StarFive JHB100 Peripheral-0 clock and reset generator Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 12/22] clk: starfive: Introduce inverter and divider Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 13/22] clk: starfive: Expand the storage of clock parent index Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 14/22] clk: starfive: Add StarFive JHB100 Peripheral-0 clock driver Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 15/22] dt-bindings: clock: Add StarFive JHB100 Peripheral-1 clock and reset generator Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 16/22] clk: starfive: Add StarFive JHB100 Peripheral-1 clock driver Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 17/22] dt-bindings: clock: Add StarFive JHB100 Peripheral-2 clock and reset generator Changhuang Liang
2026-04-04 11:34 ` Krzysztof Kozlowski
2026-04-07 1:37 ` Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 18/22] clk: starfive: Add StarFive JHB100 Peripheral-2 clock driver Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 19/22] dt-bindings: clock: Add StarFive JHB100 Peripheral-3 clock and reset generator Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 20/22] clk: starfive: Add StarFive JHB100 Peripheral-3 clock driver Changhuang Liang
2026-04-02 10:55 ` [PATCH v1 21/22] reset: starfive: Add StarFive JHB100 reset driver Changhuang Liang
2026-04-02 12:23 ` Philipp Zabel
2026-04-02 10:55 ` [PATCH v1 22/22] riscv: dts: starfive: jhb100: Add clocks and resets nodes Changhuang Liang
2026-04-02 12:14 ` Conor Dooley
2026-04-03 1:07 ` Changhuang Liang
2026-04-03 14:03 ` Conor Dooley
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