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Thu, 17 Jul 2025 12:02:08 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 56HC28sV017128 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 17 Jul 2025 12:02:08 GMT Received: from [10.216.39.173] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 17 Jul 2025 05:02:04 -0700 Message-ID: <2d5edf11-2d13-bcc7-93a9-e0a223bd6eb8@quicinc.com> Date: Thu, 17 Jul 2025 17:32:01 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH 3/3] media: iris: Add support for SM8750 (VPU v3.5) Content-Language: en-US To: Krzysztof Kozlowski , Dikshita Agarwal , Abhinav Kumar , "Bryan O'Donoghue" , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel CC: , , , References: <20250714-sm8750-iris-v1-0-3006293a5bc7@linaro.org> <20250714-sm8750-iris-v1-3-3006293a5bc7@linaro.org> <7b0a984f-b62a-ac4d-74bf-a6e839c59272@quicinc.com> <1c5df071-7000-ab45-dbc6-4384d883ba24@quicinc.com> <3a87c37b-b392-598a-736f-bb01e4c311e1@quicinc.com> From: Vikash Garodia In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=dKimmPZb c=1 sm=1 tr=0 ts=6878e640 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=ONz1pvL7zxQUDdDM2XMA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: 8qbDmR90wHf7hglQOvKe1nz6DD92OhHg X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzE3MDEwNSBTYWx0ZWRfX3a5JuebAMS5L 201l8H1DNnntdIukv+pEVAjbS8Bd1Jl0UM6z+kq7ehDFmoTONv3ZNL5ntkNVwm8zGfrU8QPW/N+ I99XOK5Cj0m/A4n5XpHje9t6xrLl15ZZDHVzE56ovn530s+m9AM+rCr/j8z9ReN6OVLgjRblMZa UZhQOxjBaz95vPBtT+fuhdDFvAWiopLPcqE3RwOfYv9ew2OS7/fYFDPg0H83AAbP/loilAq1tfZ x1yebKZI+RMtar0Q8i8+0aNt5xuKMTzBJYOJxUI/2aUPdP0jc2LdMDFtpvf3bGG6dqAMscaHS4g NSYSVdzI8ngpN5D6f0lf2M++APXSM3u/g/cVFT2X3h8I45dOGgm1HQFv2meDEs1ENNowkVfQPE8 XmNByKDWmR/rIbtHbMdLvgjw+J3Zp+BGZCB4ZSmG+UfWTur65s5aIcCnk6j0TJb5ZX3dBYza X-Proofpoint-ORIG-GUID: 8qbDmR90wHf7hglQOvKe1nz6DD92OhHg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-17_01,2025-07-17_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 mlxlogscore=848 mlxscore=0 spamscore=0 adultscore=0 impostorscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507170105 On 7/17/2025 4:24 PM, Krzysztof Kozlowski wrote: > On 17/07/2025 12:50, Dikshita Agarwal wrote: >>>>>>> + for (i = 0; i < core->iris_platform_data->num_vpp_pipe; i++) { >>>>>>> + ret = readl_poll_timeout(core->reg_base + VCODEC_SS_IDLE_STATUSN + 4 * i, >>>>>>> + val, val & 0x400000, 2000, 20000); >>>>>>> + if (ret) >>>>>>> + goto disable_power; >>>>>>> + } >>>>>>> + >>>>>>> + ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS, >>>>>>> + val, val & BIT(0), 200, 2000); >>>>>> what are you polling here for? >>>>> >>>>> >>>>> This is not different than existing code. I don't understand why you are >>>>> commenting on something which is already there. >>>> >>>> Which code are you referring to? >>> >>> To the existing vpu33 which had Reviewed-by: Vikash Garodia >>> >>> >>> You understand that everything here is the same, everything is a copy >>> while adding just few more things? >>> >>> My patch is not doing in this respect anything different that what you >>> reviewed. >>> >> >> It seems to have been missed in vpu33 power off sequence as well and should >> be fixed. >> >> Still, as mentioned earlier as well, your reference should be >> HPG/downstream driver of SM8750 not the previous generation (SM8650). > > Yes and partially no, because we write upstream code matching or > extending existing upstream driver. As you said earlier, downstream is > not the truth always: > > "That shouldn’t be the case. The downstream design is different, which > is why the driver requires the above code to move the GDSC" > > so here I built on top of SM8650 and re-iterate whatever mistakes are > there. The best if someone fixes VPU33 and then I rebase on top, > re-using fixed code as my base. You have mixed different comments made earlier. 1. Downstream GDSCs are still in HW_CTRL mode, while upstream GDSCs are migrated to HW_CTRL_TRIGGER. This does not need a fix in SM8650, but in the "iris_vpu35_power_on_hw" which you have added in this patch for SM8750. 2. Register write "AON_WRAPPER_MVP_NOC_LPI_CONTROL" with 0x1 is needed on both SM8650 and SM8750, before polling AON_WRAPPER_MVP_NOC_LPI_STATUS in "iris_vpu35_power_off_hw" function. I can soon submit a patch to fix SM8650 with the missing register write, but i do not see a need to wait for it to continue your development on SM8750. Regards, Vikash