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Fri, 16 Aug 2024 03:51:43 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 47G3pf1v006374 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 16 Aug 2024 03:51:41 GMT Received: from [10.216.10.29] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 15 Aug 2024 20:51:36 -0700 Message-ID: <2d882c88-fd56-c512-0dcc-8825ba920b51@quicinc.com> Date: Fri, 16 Aug 2024 09:21:33 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH 3/4] perf/dwc_pcie: Always register for PCIe bus notifier Content-Language: en-US To: Yicong Yang CC: Shuai Xue , Jing Zhang , Will Deacon , Mark Rutland , Baolin Wang , "Yicong Yang" , Jonathan Cameron , Jonathan Corbet , , , , , , , , , , References: <20240731-dwc_pmu_fix-v1-0-ca47d153e5b2@quicinc.com> <20240731-dwc_pmu_fix-v1-3-ca47d153e5b2@quicinc.com> <55303289-bb41-4e67-9912-4cf4335244ca@huawei.com> From: Krishna Chaitanya Chundru In-Reply-To: <55303289-bb41-4e67-9912-4cf4335244ca@huawei.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: VBabcIP9Ib1-NyQOP1j-dJZni_u4bo3j X-Proofpoint-ORIG-GUID: VBabcIP9Ib1-NyQOP1j-dJZni_u4bo3j X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-15_18,2024-08-15_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 lowpriorityscore=0 mlxlogscore=999 clxscore=1015 suspectscore=0 impostorscore=0 bulkscore=0 malwarescore=0 spamscore=0 mlxscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408160026 On 8/15/2024 7:19 PM, Yicong Yang wrote: > On 2024/7/31 12:23, Krishna chaitanya chundru wrote: >> When the PCIe devices are discovered late, the driver can't find >> the PCIe devices and returns in the init without registering with >> the bus notifier. Due to that the devices which are discovered late >> the driver can't register for this. >> >> Register for bus notifier even if the device is not found in init. >> >> Fixes: af9597adc2f1 ("drivers/perf: add DesignWare PCIe PMU driver") >> Signed-off-by: Krishna chaitanya chundru >> --- >> drivers/perf/dwc_pcie_pmu.c | 10 +++++----- >> 1 file changed, 5 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/perf/dwc_pcie_pmu.c b/drivers/perf/dwc_pcie_pmu.c >> index c115348b8d53..aa1010b44bcb 100644 >> --- a/drivers/perf/dwc_pcie_pmu.c >> +++ b/drivers/perf/dwc_pcie_pmu.c >> @@ -741,8 +741,6 @@ static int __init dwc_pcie_pmu_init(void) >> >> found = true; >> } >> - if (!found) >> - return -ENODEV; >> >> ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, >> "perf/dwc_pcie_pmu:online", >> @@ -753,9 +751,11 @@ static int __init dwc_pcie_pmu_init(void) >> >> dwc_pcie_pmu_hp_state = ret; >> >> - ret = platform_driver_register(&dwc_pcie_pmu_driver); >> - if (ret) >> - goto platform_driver_register_err; >> + if (!found) { >> + ret = platform_driver_register(&dwc_pcie_pmu_driver); >> + if (ret) >> + goto platform_driver_register_err; >> + } >> > > This doesn't match the commit. > > If any device is found at this stage, we cannot use them since you don't > register a driver. > If the device is not found then only we are skipping platform driver register otherwise driver will be registering with the platform driver. - Krishna Chaitanya. >> ret = bus_register_notifier(&pci_bus_type, &dwc_pcie_pmu_nb); >> if (ret) >>