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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-acb6eefcf37sm805661966b.97.2025.04.23.06.02.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 23 Apr 2025 06:02:49 -0700 (PDT) Message-ID: <2dae7d88-4b3e-452f-9555-05f10b42dabc@oss.qualcomm.com> Date: Wed, 23 Apr 2025 15:02:47 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: qcom: x1e80100: Add GFX power domain to GPU clock controller To: Abel Vesa , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Johan Hovold , stable@vger.kernel.org References: <20250423-x1e80100-add-gpucc-gfx-pd-v1-1-677d97f61963@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250423-x1e80100-add-gpucc-gfx-pd-v1-1-677d97f61963@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: y3wGKjWApA5dfgjh4PsQryxRb6kGAsWI X-Authority-Analysis: v=2.4 cv=ftfcZE4f c=1 sm=1 tr=0 ts=6808e4fb cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=O4X4kKYYB9jgRp4dNnsA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: y3wGKjWApA5dfgjh4PsQryxRb6kGAsWI X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDIzMDA5MCBTYWx0ZWRfXzm3wODBnGQaB +9iZOG3otXB+V8V3My8DfC/YRyMC0Bu9Y6svA+P0vP1RH3fQ7ZsO/H5JS3vrcwCCuit+lETOQK+ 4jVkiBkMNOnz2GlIkzkW0b1QF6wApAYS6fol3auyC25tIkcvdJN5hTJJNBvprgoxaIIwYnf3/DM qjZNxVXpPhPN0GWOQDg45qU0Mr8COdPmvSjdkDJ+PBcMLaw+58UhzkpTeuHVyaz9p+H0yI3+h3v shk5RHEWkeQBXTlxmL1YrXxyrz8emNn5RsTCRSAW8ybf2usvijIq4FWQlrGDqQNDe29xHfuB8im MnEcJj93YAdKwUOzYuPP7lxDxIsFFBI8OfNazoJXo+LsIOOoSGqIlbx/QH2bN6JHr72rbTx005U UMTwy0y6ye2JgE52UxFuUsZfTpAFpPanA2PozS5EJEo9YU593GabLqiHY+dBO0ztcpwTDK23 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.680,FMLib:17.12.80.40 definitions=2025-04-23_08,2025-04-22_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxscore=0 suspectscore=0 mlxlogscore=999 lowpriorityscore=0 phishscore=0 malwarescore=0 impostorscore=0 adultscore=0 spamscore=0 clxscore=1015 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504230090 On 4/23/25 2:58 PM, Abel Vesa wrote: > According to documentation, the VDD_GFX is powering up the whole GPU > subsystem. The VDD_GFX is routed through the RPMh GFX power domain. > > So tie the RPMh GFX power domain to the GPU clock controller. > > Cc: stable@vger.kernel.org # 6.11 > Fixes: 721e38301b79 ("arm64: dts: qcom: x1e80100: Add gpu support") > Signed-off-by: Abel Vesa > --- You shouldn't be messing with VDD_GFX on platforms with a GMU. Parts of the clock controller are backed by one of the MX rails, with some logic depending on CX/GFX, but handling of the latter is fully deferred to the GMU firmware. Konrad