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From: Like Xu <like.xu.linux@gmail.com>
To: Xiong Zhang <xiong.y.zhang@intel.com>
Cc: seanjc@google.com, pbonzini@redhat.com, peterz@infradead.org,
	kan.liang@linux.intel.com, zhenyuw@linux.intel.com,
	zhiyuan.lv@intel.com, kvm list <kvm@vger.kernel.org>,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/4] KVM: VMX/pmu: Enable inactive vLBR event in guest LBR MSR emulation
Date: Wed, 28 Jun 2023 13:50:46 +0800	[thread overview]
Message-ID: <2db5fe53-c316-2017-c0dc-74190d6ad9ba@gmail.com> (raw)
In-Reply-To: <20230616113353.45202-4-xiong.y.zhang@intel.com>

On 16/6/2023 7:33 pm, Xiong Zhang wrote:
> vLBR event could be inactive in two case:
> a. host per cpu pinned LBR event occupy LBR when vLBR event is created
> b. vLBR event is preempted by host per cpu pinned LBR event during vm
> exit handler.
> When vLBR event is inactive, guest couldn't access LBR msr, and it is
> forced into error state and is excluded from schedule by perf scheduler.
> So vLBR event couldn't be active through perf scheduler even if host per
> cpu pinned LBR event has released LBR, kvm could enable vLBR event
> proactively, then vLBR event may be active and LBR msr could be passthrough
> into guest.
> 
> Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com>
> ---
>   arch/x86/kvm/vmx/pmu_intel.c | 11 ++++++++++-
>   1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
> index 741efe2c497b..5a3ab8c8711b 100644
> --- a/arch/x86/kvm/vmx/pmu_intel.c
> +++ b/arch/x86/kvm/vmx/pmu_intel.c
> @@ -314,7 +314,16 @@ static bool intel_pmu_handle_lbr_msrs_access(struct kvm_vcpu *vcpu,
>   	if (!intel_pmu_is_valid_lbr_msr(vcpu, index))
>   		return false;
>   
> -	if (!lbr_desc->event && intel_pmu_create_guest_lbr_event(vcpu) < 0)
> +	/* vLBR event may be inactive, but physical LBR may be free now.
> +	 * but vLBR event is pinned event, once it is inactive state, perf
> +	 * will force it to error state in merge_sched_in() and exclude it from
> +	 * perf schedule, so even if LBR is free now, vLBR event couldn't be active
> +	 * through perf scheduler and vLBR event could be active through
> +	 * perf_event_enable().
> +	 */
> +	if (lbr_desc->event && (lbr_desc->event->state == PERF_EVENT_STATE_ERROR))
> +		perf_event_enable(lbr_desc->event);

After allowing LBR host/guest coexistence, calls perf_event_enable() for events
here do not always succeed, thus this is not a good call point.

As expected here, any erroneous perf_event is released and reprogrammed in the
kvm_pmu_handle_event(), and the perf status for enabled features are checked
near the atomic_switch_perf_msrs().

> +	else if (!lbr_desc->event && intel_pmu_create_guest_lbr_event(vcpu) < 0)
>   		goto dummy;
>   
>   	/*

  parent reply	other threads:[~2023-06-28  8:59 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-16 11:33 [PATCH 0/4] Part of fix for host and guest LBR event coexist Xiong Zhang
2023-06-16 11:33 ` [PATCH 1/4] perf/x86/intel: Get shared reg constraints first for vLBR Xiong Zhang
2023-06-28  4:25   ` Like Xu
2023-06-29  2:11     ` Zhang, Xiong Y
2023-06-16 11:33 ` [PATCH 2/4] KVM: VMX/pmu: Save host debugctlmsr just before vm entry Xiong Zhang
2023-06-23 20:15   ` Sean Christopherson
2023-06-25  4:03     ` Zhang, Xiong Y
2023-06-28  5:37       ` Like Xu
2023-06-16 11:33 ` [PATCH 3/4] KVM: VMX/pmu: Enable inactive vLBR event in guest LBR MSR emulation Xiong Zhang
2023-06-23 20:38   ` Sean Christopherson
2023-06-25  6:54     ` Zhang, Xiong Y
2023-06-26 17:00       ` Sean Christopherson
2023-06-27  3:29         ` Zhang, Xiong Y
2023-06-27 15:07           ` Sean Christopherson
2023-06-28  6:07             ` Like Xu
2023-06-28  5:50   ` Like Xu [this message]
2023-06-16 11:33 ` [PATCH 4/4] KVM: selftests: Add test case for guest and host LBR preemption Xiong Zhang
2023-06-28  6:27   ` Like Xu
2023-06-29  2:39     ` Zhang, Xiong Y
2023-06-28  9:27   ` Yang, Weijiang
2023-06-29  2:52     ` Zhang, Xiong Y
2023-06-30  2:05       ` Yang, Weijiang

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