From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from relay5-d.mail.gandi.net (relay5-d.mail.gandi.net [217.70.183.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB44B23F430 for ; Thu, 13 Feb 2025 13:02:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.197 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739451731; cv=none; b=dZwEMFivANSuVM2VdSSKfGnYDqGaeWrZZERWFHxFyQyyg4cqIYk36kmfto5ZMisQjXqn4hl0uTxcrNKKuYH/Wz/5vFvwLqnKmGDM3t758Uu2aSGbwuNpBjT6LvIkPvRsVCZuQpA57TL5VZAzu073+6MghEijawOOx2hfrN5tOtU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739451731; c=relaxed/simple; bh=qwI/dI5cmFuXSsk2MjuN08wyxIOWFu4gx+d1z5hU9Os=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=BvWCHyodXbRHHe8JC7iVo+yBCfQBlwU+Q4oOJ13kBpw+G1U5r5nIv+hxKpTKvojRqDbCkK+0DVmtWDY8m8ctdOXyegAJnh+lSXe6tQ8VHCLtiqOhvaMcno9BxvQ0BBmibhihFc+kk2wCqPQ7el1kLvrvbud1IT6wiTs2uVYdnA8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ghiti.fr; spf=pass smtp.mailfrom=ghiti.fr; arc=none smtp.client-ip=217.70.183.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ghiti.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ghiti.fr Received: by mail.gandi.net (Postfix) with ESMTPSA id A4382442D7; Thu, 13 Feb 2025 13:02:05 +0000 (UTC) Message-ID: <2db7e9ef-7566-4e86-8d5c-a3b6991e070e@ghiti.fr> Date: Thu, 13 Feb 2025 14:02:05 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/9] riscv: Fix riscv_online_cpu_vec Content-Language: en-US To: Andrew Jones , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, charlie@rivosinc.com, jesse@rivosinc.com, Anup Patel References: <20250207161939.46139-11-ajones@ventanamicro.com> <20250207161939.46139-13-ajones@ventanamicro.com> From: Alexandre Ghiti In-Reply-To: <20250207161939.46139-13-ajones@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-GND-State: clean X-GND-Score: -100 X-GND-Cause: gggruggvucftvghtrhhoucdtuddrgeefvddrtddtgdegieekfecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfitefpfffkpdcuggftfghnshhusghstghrihgsvgenuceurghilhhouhhtmecufedtudenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhepkfffgggfuffvvehfhfgjtgfgsehtjeertddtvdejnecuhfhrohhmpeetlhgvgigrnhgurhgvucfihhhithhiuceorghlvgigsehghhhithhirdhfrheqnecuggftrfgrthhtvghrnheptdfhleefjeegheevgeeljeellefgvefhkeeiffekueejteefvdevhfelvdeggeeinecukfhppedvtddtudemkeeiudemfeefkedvmegvfheltdemudgutggvmegvhedugeemheegjegvmegstdhfkeenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepihhnvghtpedvtddtudemkeeiudemfeefkedvmegvfheltdemudgutggvmegvhedugeemheegjegvmegstdhfkedphhgvlhhopeglkffrggeimedvtddtudemkeeiudemfeefkedvmegvfheltdemudgutggvmegvhedugeemheegjegvmegstdhfkegnpdhmrghilhhfrhhomheprghlvgigsehghhhithhirdhfrhdpnhgspghrtghpthhtohepkedprhgtphhtthhopegrjhhonhgvshesvhgvnhhtrghnrghmihgtrhhordgtohhmpdhrtghpthhtoheplhhinhhugidqrhhishgtvheslhhishhtshdrihhnfhhrrgguvggrugdrohhrghdprhgtphhtthhopehlihhnuhigqdhkvghrn hgvlhesvhhgvghrrdhkvghrnhgvlhdrohhrghdprhgtphhtthhopehprghulhdrfigrlhhmshhlvgihsehsihhfihhvvgdrtghomhdprhgtphhtthhopehprghlmhgvrhesuggrsggsvghlthdrtghomhdprhgtphhtthhopegthhgrrhhlihgvsehrihhvohhsihhntgdrtghomhdprhgtphhtthhopehjvghsshgvsehrihhvohhsihhntgdrtghomhdprhgtphhtthhopegrphgrthgvlhesvhgvnhhtrghnrghmihgtrhhordgtohhm X-GND-Sasl: alex@ghiti.fr On 07/02/2025 17:19, Andrew Jones wrote: > We shouldn't probe when we already know vector is unsupported and > we should probe when we see we don't yet know whether it's supported. > Furthermore, we should ensure we've set the access type to > unsupported when we don't have vector at all. > > Fixes: e7c9d66e313b ("RISC-V: Report vector unaligned access speed hwprobe") > Signed-off-by: Andrew Jones > --- > arch/riscv/kernel/unaligned_access_speed.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel/unaligned_access_speed.c > index b7a8ff7ba6df..161964cf2abc 100644 > --- a/arch/riscv/kernel/unaligned_access_speed.c > +++ b/arch/riscv/kernel/unaligned_access_speed.c > @@ -367,10 +367,12 @@ static void check_vector_unaligned_access(struct work_struct *work __always_unus > > static int riscv_online_cpu_vec(unsigned int cpu) > { > - if (!has_vector()) > + if (!has_vector()) { > + per_cpu(vector_misaligned_access, cpu) = RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED; > return 0; > + } > > - if (per_cpu(vector_misaligned_access, cpu) != RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED) > + if (per_cpu(vector_misaligned_access, cpu) != RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN) > return 0; > > check_vector_unaligned_access_emulated(NULL); Reviewed-by: Alexandre Ghiti Thanks, Alex