From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from canpmsgout04.his.huawei.com (canpmsgout04.his.huawei.com [113.46.200.219]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A97D346A04 for ; Wed, 8 Apr 2026 01:47:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.219 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775612842; cv=none; b=GBjt8UYupnevp0/bh+uvf9xZqwRT/5QsnxUIzDQvuQyQq+7j3w7P7LGYTBFDkBVitJRbx/RRvguLYhc1SOyM9gvBCAqLm+Phqh+UIfCvnl8qI/UB2wKYRT6LIY8zM++RUa5qdVPvt46vtMfmaygUACNSx67aeLQpMRGEXZr6B6M= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775612842; c=relaxed/simple; bh=VX+Z0gfQN6S9wPLeYssWP66cUY62wVn/v09ViFlAx+E=; h=Message-ID:Date:MIME-Version:Subject:To:CC:References:From: In-Reply-To:Content-Type; b=F8droyO7o6B/a2RzID9zh9QpVtKjFn01OHiVWJY14wt0uhdXo744a6mEQB4Of+8dwLL0np5+FCuteYWGBp2lJIF8pBUpPrpmcSuoSsOYan4EAARAlJX7Pks1qpiKUmbQCh+P5VhYYfCAp7bIpk2ZB8VmRBGH4TFjHitsmbDBIwc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=Q+UH9CmC; arc=none smtp.client-ip=113.46.200.219 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="Q+UH9CmC" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=+GEglMkKhZweGo4hVWdrwix8nzNduA14svrqJEyby74=; b=Q+UH9CmCywD18V8a2hz6yVw6T6oDFVuU9etvm6icu+/ZT+FdCNlOVGnmqGSKFzGqdf/FIpBKN VviI1en9jJYylAa7KTNYNW0dvgn3balkYSO4/Ww/iK71KgpZYHUoaywjhwbFoWFrqrHO+sJam+d 0cGrmivMZd50G+NMFLyzn2w= Received: from mail.maildlp.com (unknown [172.19.163.0]) by canpmsgout04.his.huawei.com (SkyGuard) with ESMTPS id 4fr5PK5Ncvz1prLF; Wed, 8 Apr 2026 09:40:53 +0800 (CST) Received: from dggpemf500011.china.huawei.com (unknown [7.185.36.131]) by mail.maildlp.com (Postfix) with ESMTPS id 717D04056D; Wed, 8 Apr 2026 09:47:10 +0800 (CST) Received: from [10.67.109.254] (10.67.109.254) by dggpemf500011.china.huawei.com (7.185.36.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Wed, 8 Apr 2026 09:47:09 +0800 Message-ID: <2de9825f-abe8-2da6-556f-2ca740f2e732@huawei.com> Date: Wed, 8 Apr 2026 09:47:07 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.2.0 Subject: Re: [PATCH 06/10] arm64: entry: Don't preempt with SError or Debug masked Content-Language: en-US To: Mark Rutland , , Catalin Marinas , Will Deacon CC: , , , , , References: <20260407131650.3813777-1-mark.rutland@arm.com> <20260407131650.3813777-7-mark.rutland@arm.com> From: Jinjie Ruan In-Reply-To: <20260407131650.3813777-7-mark.rutland@arm.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To dggpemf500011.china.huawei.com (7.185.36.131) On 2026/4/7 21:16, Mark Rutland wrote: > On arm64, involuntary kernel preemption has been subtly broken since the > move to the generic irqentry code. When preemption occurs, the new task > may run with SError and Debug exceptions masked unexpectedly, leading to > a loss of RAS events, breakpoints, watchpoints, and single-step > exceptions. > > Prior to moving to the generic irqentry code, involuntary preemption of > kernel mode would only occur when returning from regular interrupts, in > a state where interrupts were masked and all other arm64-specific > exceptions (SError, Debug, and pseudo-NMI) were unmasked. This is the > only state in which it is valid to switch tasks. > > As part of moving to the generic irqentry code, the involuntary > preemption logic was moved such that involuntary preemption could occur > when returning from any (non-NMI) exception. As most exception handlers > mask all arm64-specific exceptions before this point, preemption could > occur in a state where arm64-specific exceptions were masked. This is > not a valid state to switch tasks, and resulted in the loss of > exceptions described above. > > As a temporary bodge, avoid the loss of exceptions by avoiding > involuntary preemption when SError and/or Debug exceptions are masked. > Practically speaking this means that involuntary preemption will only > occur when returning from regular interrupts, as was the case before > moving to the generic irqentry code. > > Fixes: 99eb057ccd67 ("arm64: entry: Move arm64_preempt_schedule_irq() into __exit_to_kernel_mode()") > Reported-by: Ada Couprie Diaz > Reported-by: Vladimir Murzin > Signed-off-by: Mark Rutland > Cc: Andy Lutomirski > Cc: Catalin Marinas > Cc: Jinjie Ruan > Cc: Peter Zijlstra > Cc: Thomas Gleixner > Cc: Will Deacon > --- > arch/arm64/include/asm/entry-common.h | 21 +++++++++++++-------- > 1 file changed, 13 insertions(+), 8 deletions(-) > > diff --git a/arch/arm64/include/asm/entry-common.h b/arch/arm64/include/asm/entry-common.h > index cab8cd78f6938..20f0a7c7bde15 100644 > --- a/arch/arm64/include/asm/entry-common.h > +++ b/arch/arm64/include/asm/entry-common.h > @@ -29,14 +29,19 @@ static __always_inline void arch_exit_to_user_mode_work(struct pt_regs *regs, > > static inline bool arch_irqentry_exit_need_resched(void) > { > - /* > - * DAIF.DA are cleared at the start of IRQ/FIQ handling, and when GIC > - * priority masking is used the GIC irqchip driver will clear DAIF.IF > - * using gic_arch_enable_irqs() for normal IRQs. If anything is set in > - * DAIF we must have handled an NMI, so skip preemption. > - */ > - if (system_uses_irq_prio_masking() && read_sysreg(daif)) > - return false; > + if (system_uses_irq_prio_masking()) { > + /* > + * DAIF.DA are cleared at the start of IRQ/FIQ handling, and when GIC > + * priority masking is used the GIC irqchip driver will clear DAIF.IF > + * using gic_arch_enable_irqs() for normal IRQs. If anything is set in > + * DAIF we must have handled an NMI, so skip preemption. > + */ > + if (read_sysreg(daif)) > + return false; > + } else { > + if (read_sysreg(daif) & (PSR_D_BIT | PSR_A_BIT)) > + return false; Reviewed-by: Jinjie Ruan > + } > > /* > * Preempting a task from an IRQ means we leave copies of PSTATE