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[78.11.189.27]) by smtp.gmail.com with ESMTPSA id u15-20020ac258cf000000b00497a3e11608sm5120687lfo.303.2022.09.19.03.15.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 19 Sep 2022 03:15:52 -0700 (PDT) Message-ID: <2dfb57cd-d9d4-9a26-dd4c-f116894c9baf@linaro.org> Date: Mon, 19 Sep 2022 12:15:50 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.13.0 Subject: Re: [PATCH 1/6] dt-bindings: phy: ti: phy-gmii-sel: Add bindings for J721e Content-Language: en-US To: Siddharth Vadapalli , robh+dt@kernel.org, lee.jones@linaro.org, krzysztof.kozlowski+dt@linaro.org, kishon@ti.com, vkoul@kernel.org, dan.carpenter@oracle.com, grygorii.strashko@ti.com, rogerq@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, sjakhade@cadence.com References: <20220914093911.187764-1-s-vadapalli@ti.com> <20220914093911.187764-2-s-vadapalli@ti.com> From: Krzysztof Kozlowski In-Reply-To: <20220914093911.187764-2-s-vadapalli@ti.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 14/09/2022 11:39, Siddharth Vadapalli wrote: > TI's J721e SoC supports additional PHY modes like QSGMII and SGMII > that are not supported on earlier SoCs. Add a compatible for it. > > Extend ti,qsgmii-main-ports property to support selection of upto > two main ports at once across the two QSGMII interfaces. > > Signed-off-by: Siddharth Vadapalli > --- > .../bindings/phy/ti,phy-gmii-sel.yaml | 52 ++++++++++++++++--- > 1 file changed, 46 insertions(+), 6 deletions(-) > > diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml > index da7cac537e15..1e19efab018b 100644 > --- a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml > +++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml > @@ -54,6 +54,7 @@ properties: > - ti,dm814-phy-gmii-sel > - ti,am654-phy-gmii-sel > - ti,j7200-cpsw5g-phy-gmii-sel > + - ti,j721e-cpsw9g-phy-gmii-sel > > reg: > maxItems: 1 > @@ -65,12 +66,19 @@ properties: > description: | > Required only for QSGMII mode. Array to select the port for > QSGMII main mode. Rest of the ports are selected as QSGMII_SUB > - ports automatically. Any one of the 4 CPSW5G ports can act as the > - main port with the rest of them being the QSGMII_SUB ports. > - maxItems: 1 > - items: > - minimum: 1 > - maximum: 4 minItems: 1 maxItems: 2 items: minimum: 1 maximum: 8 > + ports automatically. For J7200 CPSW5G with the compatible: > + ti,j7200-cpsw5g-phy-gmii-sel, ti,qsgmii-main-ports is an > + array of only one element, which is the port number ranging from > + 1 to 4. For J721e CPSW9G with the compatible: > + ti,j721e-cpsw9g-phy-gmii-sel, ti,qsgmii-main-ports is an array > + of two elements, which corresponds to two potential QSGMII main > + ports. The first element and second element of the array can both > + range from 1 to 8 each, corresponding to two QSGMII main ports. > + For J721e CPSW9G, to configure port 2 as the first QSGMII main > + port and port 7 as the second QSGMII main port, we specify: > + ti,qsgmii-main-ports = <2>, <7>; > + If only one QSGMII main port is desired, mention the same main > + port twice. > > allOf: > - if: > @@ -81,12 +89,43 @@ allOf: > - ti,dra7xx-phy-gmii-sel > - ti,dm814-phy-gmii-sel > - ti,am654-phy-gmii-sel > + - ti,j7200-cpsw5g-phy-gmii-sel > + - ti,j721e-cpsw9g-phy-gmii-sel > then: > properties: > '#phy-cells': > const: 1 > description: CPSW port number (starting from 1) > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - ti,j7200-cpsw5g-phy-gmii-sel > + then: > + properties: > + ti,qsgmii-main-ports: > + maxItems: 1 > + items: > + minimum: 1 > + maximum: 4 > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - ti,j721e-cpsw9g-phy-gmii-sel > + then: > + properties: > + ti,qsgmii-main-ports: > + minItems: 2 > + maxItems: 2 > + items: > + minimum: 1 > + maximum: 8 > + > - if: > not: > properties: > @@ -94,6 +133,7 @@ allOf: > contains: > enum: > - ti,j7200-cpsw5g-phy-gmii-sel > + - ti,j721e-cpsw9g-phy-gmii-sel > then: > properties: > ti,qsgmii-main-ports: false This is interesting here... Did you test the bindings with your DTS? Best regards, Krzysztof