Re: [PATCH 1/3] perf vendor events: For the Neoverse N2

[John Garry <john.garry@huawei.com>]

On 03/12/2021 12:35, Andrew Kilroy wrote:
> Updates the common and microarch json file to add counters
> available in the Neoverse N2 chip, but should also apply to other ArmV8
> and ArmV9 cpus.  Specified in ArmV8 architecture reference manual
> 
>    https://developer.arm.com/documentation/ddi0487/gb/?lang=en
> 
> Some of the counters added to armv8-common-and-microarch.json are
> specified in the ArmV9 architecture reference manual supplement
> (issue A.a):
> 
>    https://developer.arm.com/documentation/ddi0608/aa
> 
> The additional ArmV9 counters are
> 
>    TRB_WRAP
>    TRCEXTOUT0
>    TRCEXTOUT1
>    TRCEXTOUT2
>    TRCEXTOUT3
>    CTI_TRIGOUT4
>    CTI_TRIGOUT5
>    CTI_TRIGOUT6
>    CTI_TRIGOUT7
> 
> This patch also adds files in pmu-events/arch/arm64/arm/neoverse-n2 for
> perf list to output the counter names in categories.
> 
> A subsequent patch renames armv8-common-and-microarch.json and
> armv8-recommended.json to reflect that counters for armv9 are being
> added.

This commentary should be in a cover letter. Please do that.

And did you consider just adding a armv9-common-and-microarch.json and
armv9-recommended.json instead of adding to and renaming the v8 version?
I know that it creates scattered definitions, but we already have that in
dividing the common and the recommended JSONs.

Thanks,
John