Re: [PATCH] clk: qcom: gcc-kaanapali: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock

[Taniya Das <taniya.das@oss.qualcomm.com>]

On 10/7/2026 8:07 PM, Joonhoe Kim wrote:
> As on SM8650, SM8750 and Eliza, the UFS AXI PHY clock needs
> FORCE_MEM_CORE_ON for the UFS controller in MCQ mode. Without it the MCQ
> configuration is lost over system suspend, and with MCQ enabled every
> resume from s2idle ends in an SMMU fault and a host reset.
> 
> The UFS PHY ICE core clock already has the bit set; set it for the UFS
> PHY AXI clock as well.
> 
> Fixes: d1919c375f21 ("clk: qcom: Add support for Global clock controller on Kaanapali")
> Assisted-by: LLM
> Signed-off-by: Joonhoe Kim <26rote@gmail.com>
> ---
> Tested on a Lenovo Legion Tab Y700 Gen 5 with MCQ enabled in its DT:
> the MCQ registers keep their values over s2idle, 7 of 7 resumes
> without a UFS error. Kaanapali was noted as the missing one in the
> Eliza thread [1].
> 
> [1] https://lore.kernel.org/all/a0b6030f-be42-4f5d-a59c-
> db78912ff0de@oss.qualcomm.com/
> 
>  drivers/clk/qcom/gcc-kaanapali.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/clk/qcom/gcc-kaanapali.c b/drivers/clk/qcom/gcc-kaanapali.c
> index c9473fb79ccc..6834f43b72ca 100644
> --- a/drivers/clk/qcom/gcc-kaanapali.c
> +++ b/drivers/clk/qcom/gcc-kaanapali.c
> @@ -3484,6 +3484,7 @@ static void clk_kaanapali_regs_configure(struct device *dev, struct regmap *regm
>  
>  	/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
>  	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
> +	qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
>  }
>  

Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>

-- 
Thanks,
Taniya Das