Re: [PATCH 02/11] perf/x86/intel: Update event constraints and cache_extra_regs[] for SPR

["Mi, Dapeng" <dapeng1.mi@linux.intel.com>]

On 5/20/2026 6:25 AM, Chen, Zide wrote:
>
> On 5/15/2026 11:11 PM, Dapeng Mi wrote:
>> Update perf hard-coded event constraints and cache_extra_regs[] for
>> Sapphire rapids according to the latest SPR perfmon events (v1.39).
>>
>> Emerald Rapids (EMR) and Granite Rapids (GNR) share exactly same event
>> constraints and extra MSR values with SPR. No extra changes are needed
>> for EMR and GNR.
>>
>> Please note the change could temporarily impact other platforms which
>> share the hard coded data structures, but it would be fixed in
>> subsequent patches soon.
> This may make bisection difficult. Would it be possible to reorder the
> patches to avoid this? For example, moving patch 6/11 ahead of this
> patch to avoid impacting Lunar Lake.

Hmm, it's hard to fix it by just reordering the patches. Currently the
hard-coded event data structures of previous generations would be reused by
later generations. If there are some differences between the older and
later generations, only the differences are overwritten. So even we move
the patch 6/11 ahead of this patch, it still impacts other platforms.

Besides, the "impact" here doesn't mean it must cause issues, it may fix
the incorrect hard-coded event configurations (This should be most of the
cases), sometimes the new changes may be still inaccurate for other
platforms which reuse the hard-coded event structures, but it doesn't make
things worse.

Strictly speaking, I don't think this could cause the bisection issue. For
a certain platform,  we still can figure out which commit causes the issues
by bisection.

IMO, it seems there is no way to ensure the change won't impact other
platforms except putting all changes into a single patch which is obviously
not accepted.

Thanks.


>
>> SPR perfmon events:
>> https://github.com/intel/perfmon/blob/main/SPR/events/sapphirerapids_core.json
>>
>> Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
>> ---
>>  arch/x86/events/intel/core.c | 23 ++++++++++++++---------
>>  1 file changed, 14 insertions(+), 9 deletions(-)
>>
>> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
>> index 1390d1da985b..b3ccc785a4f6 100644
>> --- a/arch/x86/events/intel/core.c
>> +++ b/arch/x86/events/intel/core.c
>> @@ -356,11 +356,12 @@ static struct extra_reg intel_glc_extra_regs[] __read_mostly = {
>>  
>>  static struct event_constraint intel_glc_event_constraints[] = {
>>  	FIXED_EVENT_CONSTRAINT(0x00c0, 0),	/* INST_RETIRED.ANY */
>> -	FIXED_EVENT_CONSTRAINT(0x0100, 0),	/* INST_RETIRED.PREC_DIST */
>> +	FIXED_EVENT_CONSTRAINT(0x0100, 0),	/* pseudo INST_RETIRED.ANY */
>>  	FIXED_EVENT_CONSTRAINT(0x003c, 1),	/* CPU_CLK_UNHALTED.CORE */
>> -	FIXED_EVENT_CONSTRAINT(0x0300, 2),	/* CPU_CLK_UNHALTED.REF */
>> +	FIXED_EVENT_CONSTRAINT(0x0200, 1),	/* pseudo CPU_CLK_UNHALTED.THREAD */
>> +	FIXED_EVENT_CONSTRAINT(0x0300, 2),	/* pseudo CPU_CLK_UNHALTED.REF_TSC */
>>  	FIXED_EVENT_CONSTRAINT(0x013c, 2),	/* CPU_CLK_UNHALTED.REF_TSC_P */
>> -	FIXED_EVENT_CONSTRAINT(0x0400, 3),	/* SLOTS */
>> +	FIXED_EVENT_CONSTRAINT(0x0400, 3),	/* pseudo TOPDOWN.SLOTS */
>>  	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
>>  	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
>>  	METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
>> @@ -380,9 +381,13 @@ static struct event_constraint intel_glc_event_constraints[] = {
>>  
>>  	INTEL_UEVENT_CONSTRAINT(0x01a3, 0xf),
>>  	INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf),
>> +	INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf),
>> +	INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf),
>>  	INTEL_UEVENT_CONSTRAINT(0x08a3, 0xf),
>> +	INTEL_UEVENT_CONSTRAINT(0x0ca3, 0xf),
>>  	INTEL_UEVENT_CONSTRAINT(0x04a4, 0x1),
>>  	INTEL_UEVENT_CONSTRAINT(0x08a4, 0x1),
>> +	INTEL_UEVENT_CONSTRAINT(0x01cd, 0xfe),
>>  	INTEL_UEVENT_CONSTRAINT(0x02cd, 0x1),
>>  	INTEL_EVENT_CONSTRAINT(0xce, 0x1),
>>  	INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xdf, 0xf),
>> @@ -714,18 +719,18 @@ static __initconst const u64 glc_hw_cache_extra_regs
>>  {
>>   [ C(LL  ) ] = {
>>  	[ C(OP_READ) ] = {
>> -		[ C(RESULT_ACCESS) ] = 0x10001,
>> -		[ C(RESULT_MISS)   ] = 0x3fbfc00001,
>> +		[ C(RESULT_ACCESS) ] = 0x10001,		/* OCR.DEMAND_DATA_RD.ANY_RESPONSE */
>> +		[ C(RESULT_MISS)   ] = 0x3fbfc00001,	/* OCR.DEMAND_DATA_RD.L3_MISS */
>>  	},
>>  	[ C(OP_WRITE) ] = {
>> -		[ C(RESULT_ACCESS) ] = 0x3f3ffc0002,
>> -		[ C(RESULT_MISS)   ] = 0x3f3fc00002,
>> +		[ C(RESULT_ACCESS) ] = 0x3f3ffc0002,	/* OCR.DEMAND_RFO.ANY_RESPONSE */
>> +		[ C(RESULT_MISS)   ] = 0x3f3fc00002,	/* OCR.DEMAND_RFO.L3_MISS */
>>  	},
>>   },
>>   [ C(NODE) ] = {
>>  	[ C(OP_READ) ] = {
>> -		[ C(RESULT_ACCESS) ] = 0x10c000001,
>> -		[ C(RESULT_MISS)   ] = 0x3fb3000001,
>> +		[ C(RESULT_ACCESS) ] = 0x104000001,	/* OCR.DEMAND_DATA_RD.LOCAL_DRAM */
>> +		[ C(RESULT_MISS)   ] = 0x730000001,	/* OCR.DEMAND_DATA_RD.REMOTE_DRAM */
>>  	},
>>   },
>>  };