From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E62BBC433FE for ; Wed, 25 May 2022 01:42:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243306AbiEYBmF (ORCPT ); Tue, 24 May 2022 21:42:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42880 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243037AbiEYBmD (ORCPT ); Tue, 24 May 2022 21:42:03 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE31B248F9; Tue, 24 May 2022 18:42:00 -0700 (PDT) X-UUID: c52bb40ef8484146b988c1131c096071-20220525 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:84804d0f-03a4-471c-95f9-d8de54f42641,OB:0,LO B:0,IP:0,URL:5,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:5 X-CID-META: VersionHash:2a19b09,CLOUDID:08045747-4fb1-496b-8f1d-39e733fed1ea,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil ,QS:0,BEC:nil X-UUID: c52bb40ef8484146b988c1131c096071-20220525 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1709642572; Wed, 25 May 2022 09:41:55 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 25 May 2022 09:41:54 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 25 May 2022 09:41:54 +0800 Message-ID: <2e5c146c53ce4d5addc05dd23e3fcd791425960c.camel@mediatek.com> Subject: Re: [PATCH v7, 3/4] drm/mediatek: keep dsi as LP00 before dcs cmds transfer From: CK Hu To: , , , , , CC: , , , , , "# 5 . 10 . x : b255d51e3967 : sched : Modify dsi funcs to atomic operations" , , Date: Wed, 25 May 2022 09:41:54 +0800 In-Reply-To: <1653012007-11854-4-git-send-email-xinlei.lee@mediatek.com> References: <1653012007-11854-1-git-send-email-xinlei.lee@mediatek.com> <1653012007-11854-4-git-send-email-xinlei.lee@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Xinlei: On Fri, 2022-05-20 at 10:00 +0800, xinlei.lee@mediatek.com wrote: > From: Jitao Shi > > To comply with the panel sequence, hold the mipi signal to LP00 > before the dcs cmds transmission, > and pull the mipi signal high from LP00 to LP11 until the start of > the dcs cmds transmission. > The normal panel timing is : > (1) pp1800 DC pull up > (2) avdd & avee AC pull high > (3) lcm_reset pull high -> pull low -> pull high > (4) Pull MIPI signal high (LP11) -> initial code -> send video > data(HS mode) > The power-off sequence is reversed. > If dsi is not in cmd mode, then dsi will pull the mipi signal high in > the mtk_output_dsi_enable function. > The delay in lane_ready func is the reaction time of dsi_rx after > pulling up the mipi signal. Reviewed-by: CK Hu > > Fixes: 2dd8075d2185 ("drm/mediatek: mtk_dsi: Use the drm_panel_bridge > API") > > Cc: # 5.10.x: b255d51e3967: sched: Modify > dsi funcs to atomic operations > Cc: # 5.10.x: 72c69c977502: sched: Separate > poweron/poweroff from enable/disable and define new funcs > Cc: # 5.10.x > Signed-off-by: Jitao Shi > Signed-off-by: Xinlei Lee > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 28 +++++++++++++++++++++------- > 1 file changed, 21 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c > b/drivers/gpu/drm/mediatek/mtk_dsi.c > index d9a6b928dba8..25e84d9426bf 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > @@ -203,6 +203,7 @@ struct mtk_dsi { > struct mtk_phy_timing phy_timing; > int refcount; > bool enabled; > + bool lanes_ready; > u32 irq_data; > wait_queue_head_t irq_wait_queue; > const struct mtk_dsi_driver_data *driver_data; > @@ -661,18 +662,11 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) > mtk_dsi_reset_engine(dsi); > mtk_dsi_phy_timconfig(dsi); > > - mtk_dsi_rxtx_control(dsi); > - usleep_range(30, 100); > - mtk_dsi_reset_dphy(dsi); > mtk_dsi_ps_control_vact(dsi); > mtk_dsi_set_vm_cmd(dsi); > mtk_dsi_config_vdo_timing(dsi); > mtk_dsi_set_interrupt_enable(dsi); > > - mtk_dsi_clk_ulp_mode_leave(dsi); > - mtk_dsi_lane0_ulp_mode_leave(dsi); > - mtk_dsi_clk_hs_mode(dsi, 0); > - > return 0; > err_disable_engine_clk: > clk_disable_unprepare(dsi->engine_clk); > @@ -701,6 +695,23 @@ static void mtk_dsi_poweroff(struct mtk_dsi > *dsi) > clk_disable_unprepare(dsi->digital_clk); > > phy_power_off(dsi->phy); > + > + dsi->lanes_ready = false; > +} > + > +static void mtk_dsi_lane_ready(struct mtk_dsi *dsi) > +{ > + if (!dsi->lanes_ready) { > + dsi->lanes_ready = true; > + mtk_dsi_rxtx_control(dsi); > + usleep_range(30, 100); > + mtk_dsi_reset_dphy(dsi); > + mtk_dsi_clk_ulp_mode_leave(dsi); > + mtk_dsi_lane0_ulp_mode_leave(dsi); > + mtk_dsi_clk_hs_mode(dsi, 0); > + msleep(20); > + /* The reaction time after pulling up the mipi signal > for dsi_rx */ > + } > } > > static void mtk_output_dsi_enable(struct mtk_dsi *dsi) > @@ -708,6 +719,7 @@ static void mtk_output_dsi_enable(struct mtk_dsi > *dsi) > if (dsi->enabled) > return; > > + mtk_dsi_lane_ready(dsi); > mtk_dsi_set_mode(dsi); > mtk_dsi_clk_hs_mode(dsi, 1); > > @@ -1017,6 +1029,8 @@ static ssize_t mtk_dsi_host_transfer(struct > mipi_dsi_host *host, > if (MTK_DSI_HOST_IS_READ(msg->type)) > irq_flag |= LPRX_RD_RDY_INT_FLAG; > > + mtk_dsi_lane_ready(dsi); > + > ret = mtk_dsi_host_send_cmd(dsi, msg, irq_flag); > if (ret) > goto restore_dsi_mode;