From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Conor Dooley <conor@kernel.org>, palmer@dabbelt.com
Cc: Conor Dooley <conor.dooley@microchip.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1] dt-bindings: riscv: permit numbers in "riscv,isa"
Date: Fri, 8 Dec 2023 19:01:13 +0100 [thread overview]
Message-ID: <2e781a85-30bc-4765-876c-28a0c2fe5cdf@linaro.org> (raw)
In-Reply-To: <20231208-uncolored-oxidant-5ab37dd3ab84@spud>
On 08/12/2023 17:06, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> There are some extensions that contain numbers, such as Zve32f, which
> are enabled by the "max" cpu type in QEMU.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
That regex exceeded my capabilities long time ago, so just formality, FWIW:
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
next prev parent reply other threads:[~2023-12-08 18:01 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-08 16:06 Conor Dooley
2023-12-08 18:01 ` Krzysztof Kozlowski [this message]
2024-01-11 14:50 ` patchwork-bot+linux-riscv
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