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From: Li Ming <ming.li@zohomail.com>
To: Dave Jiang <dave.jiang@intel.com>,
	Srirangan Madhavan <smadhavan@nvidia.com>,
	Alison Schofield <alison.schofield@intel.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	Ira Weiny <iweiny@kernel.org>,
	Jonathan Cameron <jic23@kernel.org>,
	Vishal Verma <vishal.l.verma@intel.com>,
	linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org
Cc: Joshua Machauer <machaujo@amazon.de>,
	Alex Williamson <alex.williamson@redhat.com>,
	vsethi@nvidia.com, alwilliamson@nvidia.com,
	Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
	Vishal Aslot <vaslot@nvidia.com>,
	Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
	Richard Cheng <icheng@nvidia.com>,
	linux-tegra@vger.kernel.org,
	Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
Subject: Re: [PATCH v17 02/19] cxl: Share CXL port upstream PCI device lookup
Date: Sun, 15 Nov 2026 11:25:28 +0800	[thread overview]
Message-ID: <2e8e3f34-b252-415f-8eb5-ceb1db668175@zohomail.com> (raw)
In-Reply-To: <70b69d4c-34b2-4166-9e3c-fbd9e21daf75@intel.com>

On 11/13/2026 11:50 PM, Dave Jiang wrote:
>
> On 11/10/26 6:36 AM, Li Ming wrote:
>> 在 2026/11/6 02:59, Srirangan Madhavan 写道:
>>> read_cdat_data() resolves a CXL port's upstream device to its backing PCI
>>> device. HDM cache updates need the same mapping.
>>>
>>> Factor the lookup into cxl_port_get_uport_pci_dev() and return a referenced
>>> PCI device to make caller ownership explicit.
>>>
>>> Use automatic reference cleanup in read_cdat_data(), as suggested by
>>> Li Ming, so early returns release the PCI device reference.
>>>
>>> Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
>>> Reviewed-by: Jonathan Cameron <jonathan.cameron@oss.qualcomm.com>
>>> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
>>> Reviewed-by: Richard Cheng <icheng@nvidia.com>
>>> Reviewed-by: Li Ming <ming.li@zohomail.com>
>>>
>>> ---
>>> Changes in v17:
>>> - Use an explicit pci_dev_put() on a single exit path in
>>>    read_cdat_data() instead of mixing __free() with goto cleanup
>>>    (Sashiko)
>>>    https://sashiko.dev/#/patchset/20261029145703.2185231-1-smadhavan@nvidia.com?part=2
>> Reviewed-by: Li Ming <ming.li@zohomail.com>
>>
>>
>> I still think the new goto makes the code harder to follow. But I saw your discussion in v13[1], both Jonathan and Dave agree with your current changes. I post my proposal here which can eliminate all goto labels. If there is no response from them, or if they disagree with my changes, we can continue with your implementation.
>>
>> [1]: https://lore.kernel.org/all/fb513893-7c6c-408c-811f-1eae20f0436c@intel.com/
>>
>> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
>> index 9d807c1a002c..fbf4b56a39c4 100644
>> --- a/drivers/cxl/core/pci.c
>> +++ b/drivers/cxl/core/pci.c
>> @@ -573,17 +573,8 @@ void read_cdat_data(struct cxl_port *port)
>>         size_t table_length, length;
>>         int rc;
>>
>> -       if (is_cxl_memdev(uport)) {
>> -               struct device *host;
>> -
>> -               cxlmd = to_cxl_memdev(uport);
>> -               host = cxlmd->dev.parent;
>> -               if (dev_is_pci(host))
>> -                       pdev = to_pci_dev(host);
>> -       } else if (dev_is_pci(uport)) {
>> -               pdev = to_pci_dev(uport);
>> -       }
>> -
>> +       struct pci_dev *pdev __free(pci_dev_put) =
>> +                               cxl_port_get_uport_pci_dev(port);
>>         if (!pdev)
>>                 return;
>>
>> @@ -606,30 +597,32 @@ void read_cdat_data(struct cxl_port *port)
>>          * bytes for the DOE header. Table data starts afterwards.
>>          */
>>         buf = devm_kzalloc(dev, sizeof(*buf) + length, GFP_KERNEL);
>> -       if (!buf)
>> -               goto err;
>> +       if (!buf) {
>> +               dev_err(dev, "Failed to allocate CDAT buffer.\n");
>> +               return;
>> +       }
>>
>>         table_length = length;
>>
>>         rc = cxl_cdat_read_table(dev, doe_mb, buf, &length);
>> -       if (rc)
>> -               goto err;
>> +       if (rc) {
>> +               devm_kfree(dev, buf);
>> +               dev_err(dev, "Failed to read CDAT.\n");
>> +               return;
>> +       }
>>
>>         if (table_length != length)
>>                 dev_warn(dev, "Malformed CDAT table length (%zu:%zu), discarding trailing data\n",
>>                         table_length, length);
>>
>> -       if (cdat_checksum(buf->data, length))
>> -               goto err;
>> +       if (cdat_checksum(buf->data, length)) {
>> +               devm_kfree(dev, buf);
>> +               dev_err(dev, "Failed to validate CDAT.\n");
>> +               return;
>> +       }
>>
>>         port->cdat.table = buf->data;
>>         port->cdat.length = length;
>> -
>> -       return;
>> -err:
>> -       /* Don't leave table data allocated on error */
>> -       devm_kfree(dev, buf);
>> -       dev_err(dev, "Failed to read/validate CDAT.\n");
>>  }
>>
>>
> How about something like this? I think it's cleaner:

Hi Dave,


Your implementation also works for me.


Ming

>
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index 905892cfedef..c924904faec4 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -556,6 +556,27 @@ static unsigned char cdat_checksum(void *buf, size_t size)
>  	return sum;
>  }
>  
> +static int cxl_cdat_read_validate(struct device *dev,
> +				  struct pci_doe_mb *doe_mb,
> +				  struct cdat_doe_rsp *buf, size_t *length)
> +{
> +	size_t table_length = *length;
> +	int rc;
> +
> +	rc = cxl_cdat_read_table(dev, doe_mb, buf, length);
> +	if (rc)
> +		return rc;
> +
> +	if (table_length != *length)
> +		dev_warn(dev, "Malformed CDAT table length (%zu:%zu), discarding trailing data\n",
> +			 table_length, *length);
> +
> +	if (cdat_checksum(buf->data, *length))
> +		return -EIO;
> +
> +	return 0;
> +}
> +
>  /**
>   * read_cdat_data - Read the CDAT data on this port
>   * @port: Port to read data from
> @@ -564,13 +585,13 @@ static unsigned char cdat_checksum(void *buf, size_t size)
>   */
>  void read_cdat_data(struct cxl_port *port)
>  {
> -	struct pci_dev *pdev = cxl_port_get_uport_pci_dev(port);
>  	struct device *dev = &port->dev;
>  	struct pci_doe_mb *doe_mb;
>  	struct cdat_doe_rsp *buf;
> -	size_t table_length, length;
> -	int rc;
> +	size_t length;
>  
> +	struct pci_dev *pdev __free(pci_dev_put) =
> +		cxl_port_get_uport_pci_dev(port);
>  	if (!pdev)
>  		return;
>  
> @@ -578,14 +599,14 @@ void read_cdat_data(struct cxl_port *port)
>  				      CXL_DOE_PROTOCOL_TABLE_ACCESS);
>  	if (!doe_mb) {
>  		dev_dbg(dev, "No CDAT mailbox\n");
> -		goto out;
> +		return;
>  	}
>  
>  	port->cdat_available = true;
>  
>  	if (cxl_cdat_get_length(dev, doe_mb, &length)) {
>  		dev_dbg(dev, "No CDAT length\n");
> -		goto out;
> +		return;
>  	}
>  
>  	/*
> @@ -593,31 +614,15 @@ void read_cdat_data(struct cxl_port *port)
>  	 * bytes for the DOE header. Table data starts afterwards.
>  	 */
>  	buf = devm_kzalloc(dev, sizeof(*buf) + length, GFP_KERNEL);
> -	if (!buf)
> -		goto err;
> -
> -	table_length = length;
> -
> -	rc = cxl_cdat_read_table(dev, doe_mb, buf, &length);
> -	if (rc)
> -		goto err;
> -
> -	if (table_length != length)
> -		dev_warn(dev, "Malformed CDAT table length (%zu:%zu), discarding trailing data\n",
> -			table_length, length);
> -
> -	if (cdat_checksum(buf->data, length))
> -		goto err;
> +	if (!buf || cxl_cdat_read_validate(dev, doe_mb, buf, &length)) {
> +		/* Don't leave table data allocated on error */
> +		devm_kfree(dev, buf);
> +		dev_err(dev, "Failed to read/validate CDAT.\n");
> +		return;
> +	}
>  
>  	port->cdat.table = buf->data;
>  	port->cdat.length = length;
> -	goto out;
> -err:
> -	/* Don't leave table data allocated on error */
> -	devm_kfree(dev, buf);
> -	dev_err(dev, "Failed to read/validate CDAT.\n");
> -out:
> -	pci_dev_put(pdev);
>  }
>  EXPORT_SYMBOL_NS_GPL(read_cdat_data, "CXL");



  reply	other threads:[~2026-11-15  3:26 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-05 18:58 [PATCH v17 00/19] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-11-05 18:58 ` [PATCH v17 01/19] cxl: Clarify decoder interleave limit Srirangan Madhavan
2026-11-05 18:59 ` [PATCH v17 02/19] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-11-10 13:36   ` Li Ming
2026-11-13 15:50     ` Dave Jiang
2026-11-15  3:25       ` Li Ming [this message]
2026-11-05 18:59 ` [PATCH v17 03/19] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-11-05 18:59 ` [PATCH v17 04/19] cxl: Embed decoder configuration in a standalone structure Srirangan Madhavan
2026-11-05 18:59 ` [PATCH v17 05/19] cxl: Introduce endpoint HDM decoder settings Srirangan Madhavan
2026-11-05 18:59 ` [PATCH v17 06/19] cxl: Move HDM decoder helpers to built-in code Srirangan Madhavan
2026-11-05 18:59 ` [PATCH v17 07/19] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-11-12 21:35   ` Dave Jiang
2026-11-05 18:59 ` [PATCH v17 08/19] cxl: Move cxl_rwsem into built-in code Srirangan Madhavan
2026-11-12 23:49   ` Dave Jiang
2026-11-05 18:59 ` [PATCH v17 09/19] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-11-13  0:38   ` Dave Jiang
2026-11-05 18:59 ` [PATCH v17 10/19] cxl: Build register block helpers into the kernel Srirangan Madhavan
2026-11-13 18:02   ` Dave Jiang
2026-11-05 18:59 ` [PATCH v17 11/19] PCI/CXL: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-11-10 14:12   ` Li Ming
2026-11-11  3:54     ` Li Ming
2026-11-05 18:59 ` [PATCH v17 12/19] PCI/CXL: Add CXL Device Reset sequencing Srirangan Madhavan
2026-11-10 14:29   ` Li Ming
2026-11-11 10:12   ` Lucero Palau, Alejandro
2026-11-05 18:59 ` [PATCH v17 13/19] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-11-05 18:59 ` [PATCH v17 14/19] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-11-05 18:59 ` [PATCH v17 15/19] PCI/CXL: Restore CXL state after PCI reset Srirangan Madhavan
2026-11-05 18:59 ` [PATCH v17 16/19] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-11-05 18:59 ` [PATCH v17 17/19] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
2026-11-13 17:37   ` Dave Jiang
2026-11-05 18:59 ` [PATCH v17 18/19] PCI/CXL: Flush host and device caches for " Srirangan Madhavan
2026-11-05 18:59 ` [PATCH v17 19/19] cxl: Add KUnit checks for HDM decoder unpacking Srirangan Madhavan
2026-11-05 19:31 ` [PATCH v17 00/19] PCI/CXL: Add CXL reset support for Type 2 devices Alison Schofield

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