Re: [PATCH v2] platform/x86/intel/pmc Fix Arrow Lake U/H support to intel_pmc_core driver

["Brandt, Todd E" <todd.e.brandt@intel.com>]

On Tue, 2025-05-20 at 13:15 +0300, Ilpo Järvinen wrote:
> On Fri, 16 May 2025 10:05:07 -0700, Todd Brandt wrote:
> 
> > The ARL requires that the GMA and NPU devices both be in D3Hot in
> > order
> > for PC10 and S0iX to be achieved in S2idle. The original ARL-H/U
> > addition
> > to the intel_pmc_core driver attempted to do this by switching them
> > to D3
> > in the init and resume calls of the intel_pmc_core driver.
> > 
> > The problem is the ARL-H/U have a different NPU device and thus are
> > not
> > being properly set and thus S0iX does not work properly in ARL-H/U.
> > This
> > patch creates a new ARL-H specific device id that is correct and
> > also
> > adds the D3 fixup to the suspend callback. This way if the PCI
> > devies
> > drop from D3 to D0 after resume they can be corrected for the next
> > suspend. Thus there is no dropout in S0iX.
> > 
> > [...]
> 
> 
> Thank you for your contribution, it has been applied to my local
> review-ilpo-fixes branch. Note it will show up in the public
> platform-drivers-x86/review-ilpo-fixes branch only once I've pushed
> my
> local branch there, which might take a while.

I've made one simplification that I'm about to push on Xi's suggestion.
> 
> The list of commits applied:
> [1/1] platform/x86/intel/pmc Fix Arrow Lake U/H support to
> intel_pmc_core driver
>       commit: 219aadc94ba0bddc1355ce5c5abba7fc96e758a2
> 
> --
>  i.
>