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Peter Anvin" , kys@microsoft.com, linux-hyperv@vger.kernel.org, linux-kernel@vger.kernel.org, "Long Li" , "Ingo Molnar" , "Mukesh Rathor" , "Thomas Gleixner" , "Uros Bizjak" , wei.liu@kernel.org Message-Id: <2ee05c7f-60cb-445b-b761-562385c4e6ba@app.fastmail.com> In-Reply-To: References: <20260226095056.46410-2-ardb+git@google.com> <5a2f3ffd-1692-4c32-b6f7-b94e5066dd95@citrix.com> Subject: Re: [RFT PATCH] x86/hyperv: Use __naked attribute to fix stackless C function Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Thu, 26 Feb 2026, at 14:24, Andrew Cooper wrote: > On 26/02/2026 1:07 pm, Ard Biesheuvel wrote: >> >> On Thu, 26 Feb 2026, at 13:01, Andrew Cooper wrote: >>>> @@ -133,49 +150,36 @@ static noinline void hv_crash_clear_kernpt(vo= id) * available. We restore kernel GDT, and rest of the context, and c= ontinue >>>> * to kexec. >>>> */ >>>> -static asmlinkage void __noreturn hv_crash_c_entry(void) +static v= oid >>>> __naked hv_crash_c_entry(void) { >>>> - struct hv_crash_ctxt *ctxt =3D &hv_crash_ctxt; - /* first thing= , restore kernel gdt */ >>>> - native_load_gdt(&ctxt->gdtr); + asm volatile("lgdt %0" : : "m" >>>> (hv_crash_ctxt.gdtr)); =20 >>>> - asm volatile("movw %%ax, %%ss" : : "a"(ctxt->ss)); - asm >>>> volatile("movq %0, %%rsp" : : "m"(ctxt->rsp)); + asm volatile("movw >>>> %%ax, %%ss" : : "a"(hv_crash_ctxt.ss)); + asm volatile("movq %0, >>>> %%rsp" : : "m"(hv_crash_ctxt.rsp)); >>> I know this is pre-existing, but the asm here is poor. >>> >>> All segment registers loads can have a memory operand, rather than >>> forcing through %eax, which in turn reduces the setup logic the comp= iler >>> needs to emit. >>> >>> Something like this: >>> >>> =C2=A0 =C2=A0 "movl %0, %%ss" : : "m"(hv_crash_ctxt.ss) >>> >>> ought to do. >>> >> 'movw' seems to work, yes. > > movw works, but is sub-optimal. > Can you give an asm example where movl with a segment register is accept= ed by the assembler? I only managed that with movw, hence my comment.