From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A709DC43334 for ; Fri, 10 Jun 2022 09:59:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348098AbiFJJ75 (ORCPT ); Fri, 10 Jun 2022 05:59:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43004 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347512AbiFJJ7w (ORCPT ); Fri, 10 Jun 2022 05:59:52 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7CE25B0417 for ; Fri, 10 Jun 2022 02:59:51 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id g25so5984944ejh.9 for ; Fri, 10 Jun 2022 02:59:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=message-id:date:mime-version:user-agent:subject:content-language:to :cc:references:from:in-reply-to:content-transfer-encoding; bh=gDHlNqBe4kROE4J7/F3QmWesLzxh4ZBvnILe171UGCs=; b=oDUOaXR7FzLMWZm3OxcWJ7MJl+lrNYx7qQfEIjW1VPEtcXwKo22y8LG3qxZERYh5D2 1/6bktCkaRTFXhZRPn+Tr2xjLHk2tsGAHz227PSTLTEStq6e1c1EnxqsgfASf8KpXtOL ytT4IB96hjk9kQwUL0DYslPXSmrvavbvoAF1Aasp8dsm4RIq3Ofqr0TaG8jKkL6LZoVh HlxckmQQNlM1L/ErpqkpH83MwvKjpne9sdZWGkBHCzSl4/7ohRIBcMy9tzktRd7LIJSw 2JXTjIkbSQqyAI9pB5aFcmeh+Wg5uXoi0GnkvRpd5dxQhHR8MuDnOSDfcYiOPFCbQNqo 4jYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent:subject :content-language:to:cc:references:from:in-reply-to :content-transfer-encoding; bh=gDHlNqBe4kROE4J7/F3QmWesLzxh4ZBvnILe171UGCs=; b=diGV6I2kmt/PHeo50XWzol7KukuQM6tXXGVGXO/dlMaeG6lpEMDjZEbro2A0BMuL3V JJKHvglu0LY1uRZaLBYHWEQHcUatR1ODbh8ibSyX3dfBhe7nXjVytIh2hTfzsgRPPMjA MjW0wplAb8FlQyucxuj+3r2VKG27ScSujes7KfQotm002dLy5FGIsBWksZZASSJ7xRF7 4zeWhDHD9rBzFK+FXv+Og1JldCfISIwEgiwfRJkrinGL4bVKlbdiAkRoitKAgWhRw5GV x8mkGMXDHtgWiwjQX+znO/jOvpTs/BMPBNVMhCVbmjjV1ZvL+5Pmebr/RCdQDIb/EMzq s5bA== X-Gm-Message-State: AOAM5311H6QVMjT95v0R8t7BTCVJf4vRTrFMLHuZjpIdRhqLZ3lJOwgY OVRDZRpO1iXi1cPko/Jt2GW+Ow== X-Google-Smtp-Source: ABdhPJwhGh4TDi4lutZR0Redc77UMHZsElUmLjFEgzgCSTtr0oq2PlTyBwfzFCkOUwxt2ruFoM26kA== X-Received: by 2002:a17:906:3087:b0:6f4:2901:608a with SMTP id 7-20020a170906308700b006f42901608amr40752732ejv.646.1654855189985; Fri, 10 Jun 2022 02:59:49 -0700 (PDT) Received: from [192.168.0.201] (xdsl-188-155-176-92.adslplus.ch. [188.155.176.92]) by smtp.gmail.com with ESMTPSA id en22-20020a056402529600b0043120d5f3dcsm11051751edb.14.2022.06.10.02.59.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 10 Jun 2022 02:59:49 -0700 (PDT) Message-ID: <2f386fc3-d496-62e3-20b0-ac962169e7a1@linaro.org> Date: Fri, 10 Jun 2022 11:59:47 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH v2 18/20] arm64: dts: nuvoton: Add initial NPCM8XX device tree Content-Language: en-US To: Geert Uytterhoeven , Tomer Maimon Cc: Avi Fishman , Tali Perry , Joel Stanley , Patrick Venture , Nancy Yuen , Benjamin Fair , Rob Herring , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , Philipp Zabel , Greg KH , Daniel Lezcano , Thomas Gleixner , Wim Van Sebroeck , Guenter Roeck , Catalin Marinas , Will Deacon , Arnd Bergmann , Olof Johansson , Jiri Slaby , Shawn Guo , Bjorn Andersson , Geert Uytterhoeven , Marcel Ziswiler , Vinod Koul , Biju Das , Nobuhiro Iwamatsu , Robert Hancock , =?UTF-8?Q?Jonathan_Neusch=c3=a4fer?= , Lubomir Rintel , devicetree , Linux Kernel Mailing List , linux-clk , "open list:SERIAL DRIVERS" , LINUXWATCHDOG , Linux ARM References: <20220608095623.22327-1-tmaimon77@gmail.com> <20220608095623.22327-19-tmaimon77@gmail.com> <24ad8ba0-4244-1159-328d-12d0e67951e1@linaro.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/06/2022 09:57, Geert Uytterhoeven wrote: >> "+ cpu0: cpu@0 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a35"; >> + clocks = <&clk NPCM8XX_CLK_CPU>; >> + reg = <0x0 0x0>; >> Why do you have two address cells? A bit more complicated and not >> necessary, I think." >> the arm,cortex-a35 is 64 Bit this is why we use #address-cells = <2>; >> and therefore reg = <0x0 0x0>; > > These addresses are not addresses on the main memory bus (which > is indeed 64-bit), but on the logical CPU bus. > Now, Documentation/devicetree/bindings/arm/cpus.yaml says you can > have #address-cells = <2> if you have non-zero MPIDR_EL1 high bits. > Thanks Tomer and Geert for explanation. OK for me. Best regards, Krzysztof