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Thu, 7 Aug 2025 07:21:30 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by OSA0EPF000000C8.mail.protection.outlook.com (10.167.240.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9009.8 via Frontend Transport; Thu, 7 Aug 2025 07:21:29 +0000 Received: from [172.16.64.208] (unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id CFE694160CA2; Thu, 7 Aug 2025 15:21:28 +0800 (CST) Message-ID: <2f501b15-bea3-4893-b218-ca96ff1e0561@cixtech.com> Date: Thu, 7 Aug 2025 15:21:28 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Hans Zhang Subject: Re: [PATCH v1 2/2] PCI: dwc: Fetch dedicated AER/PME interrupters To: Richard Zhu , frank.li@nxp.com, Zhiqiang.Hou@nxp.com, bhelgaas@google.com, ilpo.jarvinen@linux.intel.com, Jonthan.Cameron@huawei.com, lukas@wunner.de, feng.tang@linux.alibaba.com, jingoohan1@gmail.com, mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, robh@kernel.org Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev References: <20250807070917.2245463-1-hongxing.zhu@nxp.com> <20250807070917.2245463-3-hongxing.zhu@nxp.com> Content-Language: en-US In-Reply-To: <20250807070917.2245463-3-hongxing.zhu@nxp.com> Content-Type: text/plain; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2025 07:21:29.8415 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d32f0e3f-bf5f-4fb4-6cb1-08ddd5830790 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000C8.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SEZPR06MB7124 On 2025/8/7 15:09, Richard Zhu wrote: > EXTERNAL EMAIL > > Some PCI host bridges have limitation that AER/PME can't work over MSI. > Vendors route the AER/PME via the dedicated SPI interrupter which is > only handled by the controller driver. > > Because that aer and pme had been defined in the snps,dw-pcie.yaml > document. Fetch the vendor specific AER/PME interrupters if they are > defined in the fdt file by generic bridge->get_service_irqs hook. > > Signed-off-by: Richard Zhu > --- > .../pci/controller/dwc/pcie-designware-host.c | 32 +++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 906277f9ffaf7..9393dc99df81f 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -13,11 +13,13 @@ > #include > #include > #include > +#include > #include > #include > #include > > #include "../../pci.h" > +#include "../../pcie/portdrv.h" > #include "pcie-designware.h" > > static struct pci_ops dw_pcie_ops; > @@ -461,6 +463,35 @@ static int dw_pcie_host_get_resources(struct dw_pcie_rp *pp) > return 0; > } > > +static int dw_pcie_get_service_irqs(struct pci_host_bridge *bridge, > + int *irqs, int mask) > +{ > + struct device *dev = bridge->dev.parent; > + struct device_node *np = dev->of_node; > + int ret, count = 0; > + > + if (!np) > + return 0; > + > + if (mask & PCIE_PORT_SERVICE_AER) { > + ret = of_irq_get_byname(np, "aer"); > + if (ret > 0) { > + irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret; > + count++; > + } > + } > + > + if (mask & PCIE_PORT_SERVICE_PME) { > + ret = of_irq_get_byname(np, "pme"); > + if (ret > 0) { > + irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret; > + count++; > + } > + } > + Hi Richard, As far as I know, some SoCs directly use the misc SPI interrupt derived from Synopsys PCIe IP. This includes PME, AER and other interrupts. So here, can we assign the interrupt number ourselves? Also, whether to trigger the AER/PME interrupt in a similar way. (generic_handle_domain_irq) Because there may be a misc SPI interrupt that requires a clear related state, what is referred to here is not the AER/PME state. Best regards, Hans > + return count; > +} > + > int dw_pcie_host_init(struct dw_pcie_rp *pp) > { > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > @@ -476,6 +507,7 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) > return -ENOMEM; > > pp->bridge = bridge; > + pp->bridge->get_service_irqs = dw_pcie_get_service_irqs; > > ret = dw_pcie_host_get_resources(pp); > if (ret) > -- > 2.37.1 > >