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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTAzMDExMyBTYWx0ZWRfXybZCH+nt3xec dQHvfMDlPXNgbVHEl5Q8vx3vrLoRMBTBGcr88GGgr14g3sJNZF3pSoGUYIn1o6Aitx/vkc97zct zPbCCDldfnV6IRRM07ZViZBnvBY7deSzvIAMAKAFVMcm6dK+a7bDzafl1zjXtDyPhFZOxTMdih1 Lb+kytvMGjubWitUmA2XyT30c5XgNyenhQRGzI2/Ky5Zbt2jUFaFufkFQq1NHpU5ZCU3KzuINW6 49HrcYzzjObbRC6QyuD3LNiWJuI5kUs0u7/mYaTlPK83yxYwSxaXMfC5nth5jXSmKZPF3gP8MkN 7luP0aGQ3LgZ6m0F0OYlAyziQglaR8qUNEP15PgpHszKrMAKTlXXP/apXu+ct2LVZ8/OMnWaOiH 4qqvRm2SIMEZCnPsuHdHni6Ommp89rcHBRg3YjV0zgxB2JdjAtgY4jX9+z687tqYp2mUoh4JDdq paQ97DBticOPpl8PhPQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTAzMDExMyBTYWx0ZWRfX4bRoYvt3TRcf 7lbsZm8SuqNX9kPqPLE/WhMadP85r/1a8yeeHdZPCSeuzaCYv9q7Idub2Dcp/W5gk6KB/AMBjPO iY5ucIvRq0TsjeVIfTT5qjgsASsKZfs= X-Proofpoint-GUID: 3Jc6492kFL7D0fZTpIUi6IJjl9O8tOPn X-Proofpoint-ORIG-GUID: 3Jc6492kFL7D0fZTpIUi6IJjl9O8tOPn X-Authority-Analysis: v=2.4 cv=LZ4MLDfi c=1 sm=1 tr=0 ts=6a996ed2 cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=LVy3vgBfuOLURpGlahAA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-03_03,2026-09-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609030113 On 9/3/26 2:44 PM, Konrad Dybcio wrote: > On 9/3/26 2:19 PM, Dmitry Baryshkov wrote: >> DSI 6G v2.9 hosts (SM8650, SM8750, Kaanapali, etc.) reparent the byte and >> pixel RCGs to the DSI PHY PLL at runtime from >> dsi_link_clk_set_rate_6g_v2_9(), after the PHY has been enabled. However >> dsi_calc_clk_rate_6g() runs earlier, in order to compute the bit clock >> request for the PHY. At that point the byte RCG still has its reset >> parent (XO), so clk_round_rate() returns a bogus rate, which then ends up >> in the PHY bit clock request and the PLL gets programmed to a wrong >> frequency, breaking the panel. >> >> Move the rounding to dsi_link_clk_set_rate_6g(), which is called after >> the RCGs have been reparented to the PLL. Storing the rounded rate at >> this point still makes later link_clk_set_rate() calls no-ops in the >> CCF. Derive the byte interface clock rate from the rounded byte clock >> rate, otherwise it would keep requesting the idealized rate and >> retrigger the PLL on every transfer. >> >> Reported-by: Abel Vesa >> Reported-by: Krzysztof Kozlowski >> Fixes: 6cd33b6f4155 ("drm/msm/dsi: round 6G byte clock rate to the PLL-achievable value") >> Assisted-by: LLM >> Signed-off-by: Dmitry Baryshkov >> --- > > I don't have HW to test it on hand, but it looks good to the eye: > > Reviewed-by: Konrad Dybcio for some hw that doesn't fall into the issue that Eliza and the newer ones do anyway: Tested-by: Konrad Dybcio # SM6115P J606F Konrad