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([2a01:e0a:106d:1080:95a2:4869:9f46:45f0]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e71b728ddsm23606102f8f.9.2026.11.03.00.53.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Nov 2026 00:53:40 -0800 (PST) Message-ID: <2fdcea84-8b95-4ec1-af62-07e1803cb418@linaro.org> Date: Tue, 3 Nov 2026 09:53:39 +0100 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: neil.armstrong@linaro.org Reply-To: Neil Armstrong Subject: Re: [PATCH re-send] drm/meson: add support for higher bandwidth HDMI DTDs To: Martin Blumenstingl , linux-amlogic@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de References: <20261102212843.1213021-1-martin.blumenstingl@googlemail.com> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <20261102212843.1213021-1-martin.blumenstingl@googlemail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 11/2/26 22:28, Martin Blumenstingl wrote: > There's a report from a user with a DELL U3415W monitor and a Khadas > VIM3 stating that 3440x1440@50Hz works but 3440x1440@60Hz doesn't. > edid-decode Detailed Timing Descriptor (DTD) extract of that mode: > DTD 1: 3440x1440 59.972616 Hz 43:18 88.819 kHz 319.750000 MHz > Hfront 80 Hsync 32 Hback 48 Hpol P > Vfront 28 Vsync 10 Vback 3 Vpol N > > Those high clock rates are currently not supported by the meson_vclk > code as it limits the PLL OD (output divider) to a minimum of 2. The > formula to calculate the clock internally is (ignoring fractional > dividers): > 319.750MHz * 10 * od = 24MHz * m > > With od = 2 this results in m = 266, which is outside the supported > range of the PLL on G12A SoCs (the driver limits m to 106..247). > Using od = 2 results in m = 133, which is supported. > > Allow the driver to pick OD = 1 to gain support for modes such as > 3440x1440@60Hz. > > Link: https://forum.khadas.com/t/can-not-set-display-resolution-to-3440x1440-for-dell-monitor/26271/12 > Signed-off-by: Martin Blumenstingl > --- > Re-send of [0] which seems to have slipped through. > > > [0] https://lore.kernel.org/linux-amlogic/20260109204836.790096-1-martin.blumenstingl@googlemail.com/ > > > drivers/gpu/drm/meson/meson_vclk.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c > index dfe0c28a0f05..c0be0b7655bf 100644 > --- a/drivers/gpu/drm/meson/meson_vclk.c > +++ b/drivers/gpu/drm/meson/meson_vclk.c > @@ -700,8 +700,8 @@ static bool meson_hdmi_pll_find_params(struct meson_drm *priv, > unsigned int *frac, > unsigned int *od) > { > - /* Cycle from /16 to /2 */ > - for (*od = 16 ; *od > 1 ; *od >>= 1) { > + /* Cycle from /16 to /1 */ > + for (*od = 16 ; *od > 0 ; *od >>= 1) { > *m = meson_hdmi_pll_get_m(priv, freq * *od); > if (!*m) > continue; > @@ -750,7 +750,7 @@ static void meson_hdmi_pll_generic_set(struct meson_drm *priv, > /* OD2 goes to the PHY, and needs to be *10, so keep OD3=1 */ > od3 = 1; > if (od < 4) { > - od1 = 2; > + od1 = od; > od2 = 1; > } else { > od2 = od / 4; Reviewed-by: Neil Armstrong Thanks, Neil