From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E063C39A7FE for ; Thu, 23 Jul 2026 07:26:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784791601; cv=none; b=plqbHYG7yKkJw9NBKVh5YVtssCOiNkDDROooa4CgS6RnzwenbgYR5wmUqJZ6IflzmbHVo/mPPyNOhqZMcsitCZVepZhPTD54NIPc1Y0esiJUyIhViyQ4eE6tIHhE7VdBY68VoyR+QZrxCYnjUtaDN+q/xlxL9M46NvoAtFrYixg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784791601; c=relaxed/simple; bh=fQuZig5GU+0ps47Kg12JnM/El3X9xLJIqbg58kBalr0=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=Ks01YPxChPrD9wWruTfhYGgxNjkKnsmW3P69zowgaQgPKQzvGLkCwJ2TTuu8H9+qGbAIXWM1A5cZtbqMegR/bpNVcjBxtyfvXNcXcaajhObKXqB5QA1uef1o8jQHx5E+ViDmgEoIo9OASoPBFxhVpeNCcZi54Q2yuRR7Nkkv4tY= ARC-Authentication-Results:i=1; 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h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=bJPVYry9PIJ3A/ep4TkHZ19XXXBNH7h7R90L2lOV7qdvqmNZOu0QKcplp+57BfaMW /89CQz+bPUvnOhQlzHmX4imQRWqyTYxkB0EHPMBIulUkfkO749VvgHk/ZmVWNL7u7Y NyTTeFlBquEj44xjWAE3gQ3BamZfYXjPT+iE++yQ= Message-ID: <2fe1b74f-70b1-4b24-b416-02db6d41a6d2@arm.com> Date: Thu, 23 Jul 2026 12:56:30 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/6] arm64: cpufeature: Extend bbml2_noabort support list To: Linu Cherian , Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Suzuki K Poulose , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Gavin Shan References: <20260723044034.2983651-1-linu.cherian@arm.com> <20260723044034.2983651-4-linu.cherian@arm.com> Content-Language: en-US From: Anshuman Khandual In-Reply-To: <20260723044034.2983651-4-linu.cherian@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 23/07/26 10:10 AM, Linu Cherian wrote: > Add below cpus to the midr list, which supports > BBML2_NOABORT. > > Cortex A520(AE) > Cortex A715 > Cortex A720(AE) > Cortex A725 > Neoverse N3 > C1-Nano > C1-Pro > C1-Ultra > C1-Premium > > C1-Ultra and C1-Premium both suffer from erratum 3683289, > where Break-Before-Make must be followed to avoid a livelock. > For both CPUs, the erratum is fixed from r1p1. > Hence we do not enable BBML2_NOABORT for CPU revisions <= r1p0. > > The relevant SDENs are: > * C1-Ultra: https://developer.arm.com/documentation/111077/9-00/ > * C1-Premium: https://developer.arm.com/documentation/111078/9-00/ > > Reviewed-by: Gavin Shan > Reviewed-by: Anshuman Khandual > Signed-off-by: Linu Cherian > --- > Documentation/arch/arm64/silicon-errata.rst | 4 ++++ > arch/arm64/kernel/cpufeature.c | 10 ++++++++++ > 2 files changed, 14 insertions(+) > > diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst > index 014aa1c215a1..57c778446936 100644 > --- a/Documentation/arch/arm64/silicon-errata.rst > +++ b/Documentation/arch/arm64/silicon-errata.rst > @@ -242,10 +242,14 @@ stable kernels. > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Neoverse-V3AE | #4193784 | ARM64_ERRATUM_4118414 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | C1-Premium | #3683289 | N/A | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | C1-Premium | #4193780 | ARM64_ERRATUM_4118414 | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | C1-Pro | #4193714 | ARM64_ERRATUM_4193714 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | C1-Ultra | #3683289 | N/A | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | C1-Ultra | #4193780 | ARM64_ERRATUM_4118414 | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | MMU-500 | #562869, | ARM_SMMU_MMU_500_CPRE_ERRATA| > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 9a22df0c5120..98d2cfc2dc90 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -2152,6 +2152,16 @@ bool cpu_supports_bbml2_noabort(void) > MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), > MIDR_ALL_VERSIONS(MIDR_AMPERE1), > MIDR_ALL_VERSIONS(MIDR_AMPERE1A), > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A520AE), > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A715), > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE), > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), > + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3), > + MIDR_ALL_VERSIONS(MIDR_C1_NANO), > + MIDR_ALL_VERSIONS(MIDR_C1_PRO), > + /* Erratum 3683289 fixed in r1p1 */ > + MIDR_RANGE(MIDR_C1_ULTRA, 1, 1, 0xf, 0xf), > + MIDR_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf, 0xf), This in line with what Mark had suggested earlier. > {} > }; >