From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B0B3282F36 for ; Sun, 21 Jun 2026 13:31:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782048703; cv=none; b=Mc+PQWQdeAzmlSdTy1p1DUAXfPn7pJxIuaqzwxbNc2FCtMDxJXq6AjuuBxrMbArkVitH2ozweCEiLep+0NzsFHXGUpAcmdTOPw4FBJBmpN6CDQjoAS0G8swVJRlO4cLUU/Z8UdRyBnb3MnEex7bxNH3HQmne39OeOyiEBHLeYs4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782048703; c=relaxed/simple; bh=VN6NxdAohu577dk3D9LPn+bxrsAV8xVyAetpHGfw9H0=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=TNd9YSrByLAiI1YSWdqcKGL4hGguClJ2TGSR8ZwoamUW9iyvHXRiWIHU77gswfKBIwDqNGI2pUozkAbGdfFxf35SBhvRdwwXNH+F3ecm18s7e0BBaQsuGbmehiBHRYxUWj9vryZzXeEwRVL7lCfnQDO1YXSsTYbnyPDxWOMMvfs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=hPVl0YR9; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=JcJDzz36; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="hPVl0YR9"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="JcJDzz36" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65L9u3ji1465788 for ; Sun, 21 Jun 2026 13:31:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= UuXygAe9bgAQ+FLVDxZXXpsG+6tBLctCiBd3eYw4++U=; b=hPVl0YR9jKJ1zAf4 igC52PvK5VmgsYixYCTAuhmc9J/yLejQUpCyw7YbMKPNd6z/xT9SduM2Syxv3/LC AM/JJyA0T8GJeYqX/Yh/W4kymTCvu1wBfif1QubZIhchFg5e4I25F1yxMYWcrERQ m3QuKk3ZoQ6csiDvBhDUFioIKhaHoNIWsBQUyXez2HEeG8xIlUv5Vwm6qhgXJ0E2 SDUOKh9XJMoPm5Ew7k4mSTmiZ+eYAOFtwyMw/XEJFMKW1O6jESIUp/B3ixtN0bnm 6wB6P9PedV0/pTb3rVEpSfYrWgzDCqr6Prmmp+MaztDHrVLi8IcC40IxOIF21Gho I+KBpw== Received: from mail-pf1-f199.google.com (mail-pf1-f199.google.com [209.85.210.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ewm1k2yua-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Sun, 21 Jun 2026 13:31:41 +0000 (GMT) Received: by mail-pf1-f199.google.com with SMTP id d2e1a72fcca58-842211d6e48so3992853b3a.0 for ; Sun, 21 Jun 2026 06:31:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1782048701; x=1782653501; darn=vger.kernel.org; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=UuXygAe9bgAQ+FLVDxZXXpsG+6tBLctCiBd3eYw4++U=; b=JcJDzz36JAiPs6T5DUoZ9cyh4+O2LcZNh86e+y8gCDmbSWa6iWhZFfTy15KRd0fGpH E2R5mIKjCw5PReA2Yu3UgtIm5la0knCr7rfycsWg6CYyQZgnlsYH/z9Zo0HC90CJsXbQ I74caWTn15boJ7qEGwQyG9RbJLLcjfvzJmsmiv7hLEZN4Ik2w9Sy3Uc9BB7+3EWtq8QK Okcp6et0Nhho4dTLuLEpecF7roiid+7GaEjBXVg4hzYScpR/BR8WBmIyUhwQmLUdT0Tc o/GCECujJSInepXHD5fyqz5qZM5YTEAmr7EkgYs4whmonNehy5wUV0vpe3/+44BiWczo Fn1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782048701; x=1782653501; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-gg:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=UuXygAe9bgAQ+FLVDxZXXpsG+6tBLctCiBd3eYw4++U=; b=PeQ3kJdDo1J3liO/2+hZGhiablN0H1Oh/ZrorY+5IjUO/gWOpqkT02aNM1/Qw0rSst Z6naldDMatuax75o3ER/Lo5dorBr7BVzXWjFHavs5Hb0ljD/X0iGvuzyZnqQJlz2jKAo iJso3TvOH7UmdM0FC0Hsk+N1gSacwDf4bKh0DBvor0vhCjlSfa9Zrs5rty9GRR829fXa NXZlxicZL89TSM8edO6WckgImBW9ohzXolzueuzj4u2T29viexsDVkGSlvf9ZEBOHeWg qz1Vu8iA18MH0pq13BNjhMr5bvmD61csrsU7zyAjDNh5nviSmjzDDMS8G6oC6iiFB/C6 f5DA== X-Forwarded-Encrypted: i=1; AFNElJ+uQ4vimlPBCFM8c+q2hX7uw8PZAu9/PYn4FunLVYur9gNEDipNyOesQsaAmQiJ2kEN0ox7KHqmDHgIKp4=@vger.kernel.org X-Gm-Message-State: AOJu0YxTgik0LY6KFRzZJ04S17VnhjYvdNe4ufif3FmTrf9FL4GI2bfo pjLnzozmm+nGNYb7VTMqupkAGrqmjnQyK8AEZvbZjn0OzczmYePdK5r60iERkWyJa5LD6gVgc5t xhBGfZy3OovOn/r+J8yeuSa0jlWR+/7HcWzFyG1s6DxogQF6H7T1cNdDFvFcY/exW26A= X-Gm-Gg: AfdE7clIf0vLVFzxiiFyTyjNda2/KO1QEkTQULHWNbhIzVip0LgEhnzOi9A/USXvoop 3KHKo4TUQK/YzQjoIVxcuhbU1XIEV6nIdiD568DdG54kQOIUXY0Nfyu0ipaFMi0NDR1EdBiRKeS 9VAJAxx7RSVS1YaSsFlCwV+cHyci3liSm57ybyfCPjUBSMm6IuoVadeX3kPwYkXIbqqX+7odWe8 7lxFuWr53ooi4PtYm3Wg01KleVezlrEsBv1yBjC50rC+fH4536sGVWSJZzXHHolboJzaccoMncu 92eCo3Fktr0sEVAeMliLN2wTFoLhQFwdOyeeA7YvL110z6wpqWw2zsk/f8xWBhkkYuf9iJR3I6w aV04B7Hr+sfTid8+oi0MtYf9d6vMlofQdzu6iNyxx X-Received: by 2002:a05:6a00:2394:b0:845:4928:8645 with SMTP id d2e1a72fcca58-8455078cb38mr11154259b3a.7.1782048700850; Sun, 21 Jun 2026 06:31:40 -0700 (PDT) X-Received: by 2002:a05:6a00:2394:b0:845:4928:8645 with SMTP id d2e1a72fcca58-8455078cb38mr11154222b3a.7.1782048700418; Sun, 21 Jun 2026 06:31:40 -0700 (PDT) Received: from [192.168.29.32] ([49.43.225.115]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84564da30b5sm5058583b3a.25.2026.06.21.06.31.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 21 Jun 2026 06:31:39 -0700 (PDT) Message-ID: <2fff81bb-1880-4057-b176-dcc9e26a3527@oss.qualcomm.com> Date: Sun, 21 Jun 2026 19:01:33 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 08/13] clk: qcom: gpucc-qcm2290: Move to the latest common qcom_cc_probe() model To: Dmitry Baryshkov Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Loic Poulain , Brian Masney , Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260604-shikra-dispcc-gpucc-v4-0-8204f1029311@oss.qualcomm.com> <20260604-shikra-dispcc-gpucc-v4-8-8204f1029311@oss.qualcomm.com> <4zhwpr2n6ihjevwamqzutoyoj4owg3mkutbn3ddstooh566fqy@j2k2or3narkd> Content-Language: en-US From: Imran Shaik In-Reply-To: <4zhwpr2n6ihjevwamqzutoyoj4owg3mkutbn3ddstooh566fqy@j2k2or3narkd> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: 4VXWW4pd93ydlsvWPdt0WT605O4__rpE X-Proofpoint-Spam-Info: AW1haW4tMjYwNjIxMDEzNyBTYWx0ZWRfXyVJPLAil8dkb ZVe3jse5OmauwM2hXh7GBKTC9zvaO9gj22uNbmeC1GTor0zWJ/BYpbVJSPagZRfcj1dmVtxdtng V8vmyADQdfMtnIUTLk8YXFIE3IiDUJ0= X-Authority-Analysis: v=2.4 cv=T6S8ifKQ c=1 sm=1 tr=0 ts=6a37e7bd cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=HwFTmRh04JSsUSWzyQ2edw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=D-w674G2B0HpSMWNuX0A:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjIxMDEzNyBTYWx0ZWRfXzIhTpI61Z8xI 6aRG+TdFtjnoR7IiGCwF/zwxWuDy90un2jnEnMwr9JjP5+NuRpyTEY+seOIVXcFVUh02AAktaC/ aWG8itk8rAt/tGo8vmsS9I1SnoIAPwM6meNJFRcfspwviwMf4/YgPTvxfJxhv8yKKPb7V0j63ts ryZnuqz5EQRBLP02dHtNTZQIomKio/1gShxgnHLCZav8gBTVb3jnaSML7PgVSpE2PC7Kkei14Xb ud//H87Ka0W+jmVO1teYlo7J/HnVjDFdzmZDOVFAuoUpdydJs3y5Z8YxcJP/RA5axi2W59nFNVg 86jW+uH/nlIEO/BmE1ZSjCfXq1bDo634ZQZhFJgpgxuhrjbTWIC1tHFH9P1/EiQZsIeNy/NtJ/h VLnkt6UG7krljNKc0lF/XtXp+722fhUadMOMNzEvFyxlzUjdzRl7IT3og5EkIekaxzNKcLm6UT0 xmvX9CRE7IAcNwMzFlg== X-Proofpoint-ORIG-GUID: 4VXWW4pd93ydlsvWPdt0WT605O4__rpE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-21_01,2026-06-18_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 malwarescore=0 adultscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606210137 On 06-06-2026 04:59 pm, Dmitry Baryshkov wrote: > On Thu, Jun 04, 2026 at 10:56:14AM +0530, Imran Shaik wrote: >> Update the QCM2290 GPUCC driver to use the qcom_cc_probe() model by moving >> the critical clocks handling and PLL configurations from probe to the >> driver_data to align with the latest convention. While at it, drop the >> modelling of gpu_cc_ahb_clk and gpu_cc_cxo_aon_clk clocks and keep them > > Why? Also it looks like a separate commit to me. > Sure, I will check and split the patches. >> enabled from probe as per the hardware requirements, and drop pm_clk >> handling as the required GCC clocks are kept always-on from GCC probe. > > Separate commit. > Sure. >> >> Signed-off-by: Imran Shaik >> --- >> drivers/clk/qcom/gpucc-qcm2290.c | 92 +++++++++------------------------------- >> 1 file changed, 21 insertions(+), 71 deletions(-) >> >> @@ -224,19 +210,6 @@ static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { >> }, >> }; >> >> -static struct clk_branch gpu_cc_cxo_aon_clk = { >> - .halt_reg = 0x1004, >> - .halt_check = BRANCH_HALT_DELAY, >> - .clkr = { >> - .enable_reg = 0x1004, >> - .enable_mask = BIT(0), >> - .hw.init = &(struct clk_init_data){ >> - .name = "gpu_cc_cxo_aon_clk", >> - .ops = &clk_branch2_ops, >> - }, >> - }, >> -}; > > This wasn't always-on beforehand. Why is being changed? > >> - >> static struct clk_branch gpu_cc_cxo_clk = { >> .halt_reg = 0x109c, >> .halt_check = BRANCH_HALT, >> @@ -318,12 +291,10 @@ static struct gdsc gpu_gx_gdsc = { >> }; >> >> static struct clk_regmap *gpu_cc_qcm2290_clocks[] = { >> - [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, >> [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, >> [GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr, >> [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, >> [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, >> - [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, >> [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, >> [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, >> [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr, >> @@ -342,6 +313,16 @@ static struct gdsc *gpu_cc_qcm2290_gdscs[] = { >> [GPU_GX_GDSC] = &gpu_gx_gdsc, >> }; >> >> +static struct clk_alpha_pll *gpu_cc_qcm2290_plls[] = { >> + &gpu_cc_pll0, >> +}; >> + >> +static const u32 gpu_cc_qcm2290_critical_cbcrs[] = { >> + 0x1078, /* GPU_CC_AHB_CLK */ >> + 0x1004, /* GPU_CC_CXO_AON_CLK */ >> + 0x1060, /* GPU_CC_GX_CXO_CLK */ >> +}; >> + >> static const struct regmap_config gpu_cc_qcm2290_regmap_config = { >> .reg_bits = 32, >> .reg_stride = 4, >> @@ -350,6 +331,12 @@ static const struct regmap_config gpu_cc_qcm2290_regmap_config = { >> .fast_io = true, >> }; >> >> +static const struct qcom_cc_driver_data gpu_cc_qcm2290_driver_data = { >> + .alpha_plls = gpu_cc_qcm2290_plls, >> + .num_alpha_plls = ARRAY_SIZE(gpu_cc_qcm2290_plls), >> + .clk_cbcrs = gpu_cc_qcm2290_critical_cbcrs, >> + .num_clk_cbcrs = ARRAY_SIZE(gpu_cc_qcm2290_critical_cbcrs), >> +}; >> >> static const struct qcom_cc_desc gpu_cc_qcm2290_desc = { >> .config = &gpu_cc_qcm2290_regmap_config, >> @@ -359,6 +346,7 @@ static const struct qcom_cc_desc gpu_cc_qcm2290_desc = { >> .num_resets = ARRAY_SIZE(gpu_cc_qcm2290_resets), >> .gdscs = gpu_cc_qcm2290_gdscs, >> .num_gdscs = ARRAY_SIZE(gpu_cc_qcm2290_gdscs), >> + .driver_data = &gpu_cc_qcm2290_driver_data, >> }; >> >> static const struct of_device_id gpu_cc_qcm2290_match_table[] = { >> @@ -369,45 +357,7 @@ MODULE_DEVICE_TABLE(of, gpu_cc_qcm2290_match_table); >> >> static int gpu_cc_qcm2290_probe(struct platform_device *pdev) >> { >> - struct regmap *regmap; >> - int ret; >> - >> - regmap = qcom_cc_map(pdev, &gpu_cc_qcm2290_desc); >> - if (IS_ERR(regmap)) >> - return PTR_ERR(regmap); >> - >> - ret = devm_pm_runtime_enable(&pdev->dev); > > So, it was pm_runtime-enabled beforehand. Now you've silently dropped > it. > My bad, will add use_rpm flag. Thanks, Imran