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Oktober 2026, 11:17:08 Mitteleurop=C3=A4ische Normalzeit s= chrieb Krzysztof Kozlowski: > On Mon, Oct 26, 2026 at 02:56:47PM +0800, Cunhao Lu wrote: > > From: Elaine Zhang > >=20 > > The RK3572 CRU uses the PMU0 GRF for the AUPLL reference mux. > > Describe the controller and define its clock and reset IDs. > >=20 > > Signed-off-by: Elaine Zhang > >=20 > > - Documented the xin24m input. > > - Made the PMU0 GRF phandle required. > > - Updated the example. > > - Closed the reset ID gap while preserving each named reset's register > > mapping. > > - Removed CLK_NR_CLKS from the clock binding. > >=20 >=20 > All your patches seems to have odd commit msg. >=20 > > Signed-off-by: Cunhao Lu <1579567540@qq.com> With code originating in the vendor kernel, it is nice to know what changed, but I guess there is a tradeoff between brevity and more details. I guess this could be shorted to something less verbose, like +++++++++++++ Signed-off-by: Elaine Zhang [adapted to mainline rockchip clock and reset handling (xin24m input, don't introduce CLK_NR_CLKS, etc ] Signed-off-by: Cunhao Lu <1579567540@qq.com> +++++++++++++