From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI, NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83A47C433E0 for ; Mon, 1 Feb 2021 11:40:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3FD8164E9B for ; Mon, 1 Feb 2021 11:40:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229927AbhBALjw (ORCPT ); Mon, 1 Feb 2021 06:39:52 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:11965 "EHLO szxga06-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229495AbhBALjs (ORCPT ); Mon, 1 Feb 2021 06:39:48 -0500 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4DTmCZ2P9TzjGDg; Mon, 1 Feb 2021 19:38:02 +0800 (CST) Received: from [127.0.0.1] (10.174.176.220) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.498.0; Mon, 1 Feb 2021 19:38:57 +0800 Subject: Re: [PATCH v6 4/4] ARM: Add support for Hisilicon Kunpeng L3 cache controller To: Arnd Bergmann CC: Russell King , Greg Kroah-Hartman , Will Deacon , "Haojian Zhuang" , Arnd Bergmann , Rob Herring , Wei Xu , devicetree , linux-arm-kernel , linux-kernel References: <20210201033601.1642-1-thunder.leizhen@huawei.com> <20210201033601.1642-5-thunder.leizhen@huawei.com> From: "Leizhen (ThunderTown)" Message-ID: <301c82eb-68ce-1a96-a0b8-d46a29bf6f36@huawei.com> Date: Mon, 1 Feb 2021 19:38:56 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.174.176.220] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2021/2/1 16:31, Arnd Bergmann wrote: > On Mon, Feb 1, 2021 at 4:36 AM Zhen Lei wrote: >> >> Add support for the Hisilicon Kunpeng L3 cache controller as used with >> Kunpeng506 and Kunpeng509 SoCs. >> >> These Hisilicon SoCs support LPAE, so the physical addresses is wider than >> 32-bits, but the actual bit width does not exceed 36 bits. When the cache >> operation is performed based on the address range, the upper 30 bits of >> the physical address are recorded in registers L3_MAINT_START and >> L3_MAINT_END, and ignore the lower 6 bits cacheline offset. >> >> Signed-off-by: Zhen Lei > > Reviewed-by: Arnd Bergmann > > If you add one more thing: > >> +static void l3cache_maint_common(u32 range, u32 op_type) >> +{ >> + u32 reg; >> + >> + reg = readl_relaxed(l3_ctrl_base + L3_MAINT_CTRL); >> + reg &= ~(L3_MAINT_RANGE_MASK | L3_MAINT_TYPE_MASK); >> + reg |= range | op_type; >> + reg |= L3_MAINT_STATUS_START; >> + writel(reg, l3_ctrl_base + L3_MAINT_CTRL); >> + >> + /* Wait until the hardware maintenance operation is complete. */ >> + do { >> + cpu_relax(); >> + reg = readl(l3_ctrl_base + L3_MAINT_CTRL); >> + } while ((reg & L3_MAINT_STATUS_MASK) != L3_MAINT_STATUS_END); >> +} >> + >> +static void l3cache_maint_range(phys_addr_t start, phys_addr_t end, u32 op_type) >> +{ >> + start = start >> L3_CACHE_LINE_SHITF; >> + end = ((end - 1) >> L3_CACHE_LINE_SHITF) + 1; >> + >> + writel_relaxed(start, l3_ctrl_base + L3_MAINT_START); >> + writel_relaxed(end, l3_ctrl_base + L3_MAINT_END); >> + >> + l3cache_maint_common(L3_MAINT_RANGE_ADDR, op_type); >> +} > > As mentioned, I'd like to see a code comment that explains the use > the of relaxed() vs non-relaxed MMIO accessors, as it will be impossible > for a reader to later understand why you picked a mix of the two, > and it also ensures that you have considered which one is the best > option to use here and that your explanation matches what you do. OK, I'll test the performance and add the comment. > > Based on Russell's comments, I had expected that you would use > only relaxed accessors, plus explicit barriers if you change it, matching > what l2x0 does (l2x0 has to do it because of __l2c210_cache_sync(), > while you don't have a sync callback and don't need to). I might have been a little conservative, I'll change all of them to _relaxed and then test it. Thanks. > > Arnd > > . >