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Wed, 19 Mar 2025 10:16:12 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 52JAGBMw002837 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 19 Mar 2025 10:16:11 GMT Received: from [10.216.37.197] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 19 Mar 2025 03:16:03 -0700 Message-ID: <303194d4-d342-ea4c-0bb6-5f5d0297ba23@quicinc.com> Date: Wed, 19 Mar 2025 15:46:00 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v4 02/10] arm64: dts: qcom: qcs6490-rb3gen2: Add TC956x PCIe switch node Content-Language: en-US To: Dmitry Baryshkov CC: Krishna Chaitanya Chundru , "Bjorn Helgaas" , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Manivannan Sadhasivam , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Bjorn Andersson" , Konrad Dybcio , , Jingoo Han , Bartosz Golaszewski , , , , , , , , References: <20250225-qps615_v4_1-v4-0-e08633a7bdf8@oss.qualcomm.com> <20250225-qps615_v4_1-v4-2-e08633a7bdf8@oss.qualcomm.com> <8a2bce29-95dc-53b0-0516-25a380d94532@oss.qualcomm.com> <16a9ff11-70dc-22e9-bd3c-ed10bf8b4fea@quicinc.com> From: Krishna Chaitanya Chundru In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=H8Pbw/Yi c=1 sm=1 tr=0 ts=67da996c cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=arMFPUd-6P6zm0bSz1oA:9 a=QEXdDO2ut3YA:10 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: KV2koTMloLA6pRaNOAbT0W_FaxPQ0j5G X-Proofpoint-ORIG-GUID: KV2koTMloLA6pRaNOAbT0W_FaxPQ0j5G X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-19_03,2025-03-19_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 lowpriorityscore=0 bulkscore=0 adultscore=0 spamscore=0 priorityscore=1501 mlxscore=0 suspectscore=0 malwarescore=0 clxscore=1015 impostorscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503190071 On 3/19/2025 3:43 PM, Dmitry Baryshkov wrote: > On Wed, Mar 19, 2025 at 09:14:22AM +0530, Krishna Chaitanya Chundru wrote: >> >> >> On 3/18/2025 10:30 PM, Dmitry Baryshkov wrote: >>> On Tue, 18 Mar 2025 at 18:11, Krishna Chaitanya Chundru >>> wrote: >>>> >>>> >>>> >>>> On 3/17/2025 4:57 PM, Dmitry Baryshkov wrote: >>>>> On Tue, Feb 25, 2025 at 03:03:59PM +0530, Krishna Chaitanya Chundru wrote: >>>>>> Add a node for the TC956x PCIe switch, which has three downstream ports. >>>>>> Two embedded Ethernet devices are present on one of the downstream ports. >>>>>> >>>>>> Power to the TC956x is supplied through two LDO regulators, controlled by >>>>>> two GPIOs, which are added as fixed regulators. Configure the TC956x >>>>>> through I2C. >>>>>> >>>>>> Signed-off-by: Krishna Chaitanya Chundru >>>>>> Reviewed-by: Bjorn Andersson >>>>>> Acked-by: Manivannan Sadhasivam >>>>>> --- >>>>>> arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 116 +++++++++++++++++++++++++++ >>>>>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- >>>>>> 2 files changed, 117 insertions(+), 1 deletion(-) >>>>>> >>>>>> @@ -735,6 +760,75 @@ &pcie1_phy { >>>>>> status = "okay"; >>>>>> }; >>>>>> >>>>>> +&pcie1_port { >>>>>> + pcie@0,0 { >>>>>> + compatible = "pci1179,0623", "pciclass,0604"; >>>>>> + reg = <0x10000 0x0 0x0 0x0 0x0>; >>>>>> + #address-cells = <3>; >>>>>> + #size-cells = <2>; >>>>>> + >>>>>> + device_type = "pci"; >>>>>> + ranges; >>>>>> + bus-range = <0x2 0xff>; >>>>>> + >>>>>> + vddc-supply = <&vdd_ntn_0p9>; >>>>>> + vdd18-supply = <&vdd_ntn_1p8>; >>>>>> + vdd09-supply = <&vdd_ntn_0p9>; >>>>>> + vddio1-supply = <&vdd_ntn_1p8>; >>>>>> + vddio2-supply = <&vdd_ntn_1p8>; >>>>>> + vddio18-supply = <&vdd_ntn_1p8>; >>>>>> + >>>>>> + i2c-parent = <&i2c0 0x77>; >>>>>> + >>>>>> + reset-gpios = <&pm8350c_gpios 1 GPIO_ACTIVE_LOW>; >>>>>> + >>>>> >>>>> I think I've responded here, but I'm not sure where the message went: >>>>> please add pinctrl entry for this pin. >>>>> >>>> Do we need to also add pinctrl property for this node and refer the >>>> pinctrl entry for this pin? >>> >>> I think that is what I've asked for, was that not? >> Currently there is no pincntrl property defined for this. > > Does it need to be defined separately / specially? > yes we need to define this property now. - Krishna Chaitanya.