Re: [PATCH v1] KVM: x86: expose AVX512_BF16 feature to guest

[Paolo Bonzini <pbonzini@redhat.com>]

On 11/07/19 07:49, Jing Liu wrote:
> AVX512 BFLOAT16 instructions support 16-bit BFLOAT16 floating-point
> format (BF16) for deep learning optimization.
> 
> Intel adds AVX512 BFLOAT16 feature in CooperLake, which is CPUID.7.1.EAX[5].
> 
> Detailed information of the CPUID bit can be found here,
> https://software.intel.com/sites/default/files/managed/c5/15/\
> architecture-instruction-set-extensions-programming-reference.pdf.
> 
> Signed-off-by: Jing Liu <jing2.liu@linux.intel.com>
> ---
> 
> This patch depends on kernel patch https://lkml.org/lkml/2019/6/19/912
> and Paolo's patch set https://lkml.org/lkml/2019/7/4/468.
> 
>  arch/x86/kvm/cpuid.c | 12 +++++++++++-
>  1 file changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
> index 8fc6039..0c125dd 100644
> --- a/arch/x86/kvm/cpuid.c
> +++ b/arch/x86/kvm/cpuid.c
> @@ -358,9 +358,13 @@ static inline void do_cpuid_7_mask(struct kvm_cpuid_entry2 *entry, int index)
>  		F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
>  		F(MD_CLEAR);
>  
> +	/* cpuid 7.1.eax */
> +	const u32 kvm_cpuid_7_1_eax_x86_features =
> +		F(AVX512_BF16);
> +
>  	switch (index) {
>  	case 0:
> -		entry->eax = 0;
> +		entry->eax = min(entry->eax, 1);
>  		entry->ebx &= kvm_cpuid_7_0_ebx_x86_features;
>  		cpuid_mask(&entry->ebx, CPUID_7_0_EBX);
>  		/* TSC_ADJUST is emulated */
> @@ -384,6 +388,12 @@ static inline void do_cpuid_7_mask(struct kvm_cpuid_entry2 *entry, int index)
>  		 */
>  		entry->edx |= F(ARCH_CAPABILITIES);
>  		break;
> +	case 1:
> +		entry->eax &= kvm_cpuid_7_1_eax_x86_features;
> +		entry->ebx = 0;
> +		entry->ecx = 0;
> +		entry->edx = 0;
> +		break;
>  	default:
>  		WARN_ON_ONCE(1);
>  		entry->eax = 0;
> 

Queued, thanks.

Paolo