From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D07EAC07545 for ; Wed, 25 Oct 2023 11:26:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343545AbjJYL0x (ORCPT ); Wed, 25 Oct 2023 07:26:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45748 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234703AbjJYL0s (ORCPT ); Wed, 25 Oct 2023 07:26:48 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 21596137; Wed, 25 Oct 2023 04:26:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698233207; x=1729769207; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=U898RgRa9XJVhqUowGUXC2Jsf0LatDtgPXZQS2KdZeI=; b=iF14QKz2tDt3iZ9VMp7u6bPtqI2PKFZ6iuO80l5FkwGmIYI8WswE6qTB FZIeCqHOQeThBq06dQBBEuVzToKhozWDjWegTH8y2CkfZBOOn0CR9G2RU X+Nj/3jL/SKOMrhSwxnPzedmay5eVjXwoMFz5PZAEfCQ9ovTrwK6BEUBO XHyQIPLOGZ8Bo2bWHE6W64pkI0QMjRSZMgvwikgOKkuVAiQ10e0UrvSTE LCkDWFZefRMA4GyEdrZYqQW7+Nr0C6T6/L+d2dt50pXR2/ZcHDp5B51IN kIgOuRXJ8TJExh9fSe5oo+mYvsy1ogxkBu5duhqHbcmooOHGPzSv7XhZN Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10873"; a="8846492" X-IronPort-AV: E=Sophos;i="6.03,250,1694761200"; d="scan'208";a="8846492" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2023 04:26:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,250,1694761200"; d="scan'208";a="6812800" Received: from dapengmi-mobl1.ccr.corp.intel.com (HELO [10.93.25.165]) ([10.93.25.165]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Oct 2023 04:26:36 -0700 Message-ID: <305f1ee4-a8c3-48eb-9368-531329e5266e@linux.intel.com> Date: Wed, 25 Oct 2023 19:26:41 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [kvm-unit-tests Patch 4/5] x86: pmu: Support validation for Intel PMU fixed counter 3 Content-Language: en-US To: Jim Mattson Cc: Sean Christopherson , Paolo Bonzini , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhenyu Wang , Zhang Xiong , Mingwei Zhang , Like Xu , Dapeng Mi References: <20231024075748.1675382-1-dapeng1.mi@linux.intel.com> <20231024075748.1675382-5-dapeng1.mi@linux.intel.com> From: "Mi, Dapeng" In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/25/2023 3:05 AM, Jim Mattson wrote: > On Tue, Oct 24, 2023 at 12:51 AM Dapeng Mi wrote: >> Intel CPUs, like Sapphire Rapids, introduces a new fixed counter >> (fixed counter 3) to counter/sample topdown.slots event, but current >> code still doesn't cover this new fixed counter. >> >> So add code to validate this new fixed counter. > Can you explain how this "validates" anything? I may not describe the sentence clearly. This would validate the fixed counter 3 can count the slots event and get a valid count in a reasonable range. Thanks. > >> Signed-off-by: Dapeng Mi >> --- >> x86/pmu.c | 3 ++- >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> diff --git a/x86/pmu.c b/x86/pmu.c >> index 1bebf493d4a4..41165e168d8e 100644 >> --- a/x86/pmu.c >> +++ b/x86/pmu.c >> @@ -46,7 +46,8 @@ struct pmu_event { >> }, fixed_events[] = { >> {"fixed 1", MSR_CORE_PERF_FIXED_CTR0, 10*N, 10.2*N}, >> {"fixed 2", MSR_CORE_PERF_FIXED_CTR0 + 1, 1*N, 30*N}, >> - {"fixed 3", MSR_CORE_PERF_FIXED_CTR0 + 2, 0.1*N, 30*N} >> + {"fixed 3", MSR_CORE_PERF_FIXED_CTR0 + 2, 0.1*N, 30*N}, >> + {"fixed 4", MSR_CORE_PERF_FIXED_CTR0 + 3, 1*N, 100*N} >> }; >> >> char *buf; >> -- >> 2.34.1 >>