From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751159AbdAMGLz (ORCPT ); Fri, 13 Jan 2017 01:11:55 -0500 Received: from mail-qk0-f194.google.com ([209.85.220.194]:34947 "EHLO mail-qk0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750749AbdAMGLx (ORCPT ); Fri, 13 Jan 2017 01:11:53 -0500 From: Len Brown To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, Len Brown Subject: [PATCH] x86 tsc: Add the Intel Denverton Processor to native_calibrate_tsc() Date: Fri, 13 Jan 2017 01:11:18 -0500 Message-Id: <306899f94804aece6d8fa8b4223ede3b48dbb59c.1484287748.git.len.brown@intel.com> X-Mailer: git-send-email 2.11.0.161.g6610af872 Reply-To: Len Brown Organization: Intel Open Source Technology Center Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Len Brown The Intel Denverton microserver uses a 25 MHz TSC crystal, so we can derive its exact * TSC frequency using CPUID and some arithmetic, eg. TSC: 1800 MHz (25000000 Hz * 216 / 3 / 1000000) * 'exact' is only as good as the crystal, which should be +/- 20ppm Signed-off-by: Len Brown --- arch/x86/kernel/tsc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 46b2f41f8b05..b3e397a0f29d 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -694,6 +694,7 @@ unsigned long native_calibrate_tsc(void) crystal_khz = 24000; /* 24.0 MHz */ break; case INTEL_FAM6_SKYLAKE_X: + case INTEL_FAM6_ATOM_DENVERTON: crystal_khz = 25000; /* 25.0 MHz */ break; case INTEL_FAM6_ATOM_GOLDMONT: -- 2.11.0.161.g6610af872