Re: [PATCH v5 5/6] clk: fsl-sai: Extract clock setup into fsl_sai_clk_register()

[Marek Vasut <marex@nabladev.com>]

On 4/9/26 12:12 AM, Brian Masney wrote:

Hi,

>> -	hw = devm_clk_hw_register_composite_pdata(dev, dev->of_node->name,
>> -						  &pdata, 1, NULL, NULL,
>> -						  &sai_clk->div.hw,
>> -						  &clk_divider_ops,
>> -						  &sai_clk->gate.hw,
>> -						  &clk_gate_ops,
>> -						  CLK_SET_RATE_GATE);
>> -	if (IS_ERR(hw))
>> -		return PTR_ERR(hw);
>> -
>> -	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
>> +	ret = fsl_sai_clk_register(dev, base, &sai_clk->lock,
>> +				   &sai_clk->bclk_div, &sai_clk->bclk_gate,
>> +				   &sai_clk->bclk_hw, CSR_BCE_BIT, CR2_BCD,
>> +				   data->offset + I2S_CR2, "BCLK");
>                                     ^^^^^^^^^^^^^^^^^^^^^^
> Sashiko reports the following:
> https://sashiko.dev/#/patchset/20260407211123.77602-1-marex%40nabladev.com
> 
>      For MCLK, this evaluates to writel(MCR_MOE, base + I2S_MCR). Does this
>      overwrite the entire register and clear all other bits to 0? This could zero
>      out fields like the MCLK Divider Enable and Clock Source Select, breaking
>      the MCLK hardware divider.
> 
> It's the same behavior as what was there previously. There's a lot more
> to the comment. Can you look and see if there's anything else valid in
> Sashiko's comment that should be addressed while changes are being made
> here?
> 
> Otherwise, based on what was there previously, this looks good to me.
I'll move the writel() before devm_clk_hw_register_composite_pdata() 
even if it makes no difference in this particular case.