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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI0MDA4MiBTYWx0ZWRfX3ANMuiJ8I9Wl rtBDZjOgS+ba4kr1BWCj0HNCdayCfXbGjX4xnXkPuqLirWg5KY1EwQuQbdpcTIYVwLX1qKjQ23g DQGcFUHnv/fF3+ddy9ojedGDgH/sJQ3SQthggbBjVLTGiiDQyfCZd3kwg13JqV8OFgwDwaC4Q+B yB7FUauQqlhXZxDmsfo9N90SahfdZU6X1vL3kXitOmWr7YeculkZmfcazl695MLAC+EwmfRDG4l BodlSofkgCfpg9XhAMZ65y6m0QEw4dEwfe8uQTp/b1X/6l0GLbJL+hoWvKBjW8IByGK095zRnmS iXtZfoTh+JSFLY+QirIlf4R1M5fCPy9TH/TZPYG3GVBqxWF0tc1DrbXE3rk/nIiTA5zE8t0R/d9 sSJMbOKCVu/mWwuBkkigDMJiedzznPG6TMbJwm1SG+V8ZrIpAOMKYCrvUY1ykWq4jRpuzwG+w/s 7RIAYM4wKKUxAaDppag== X-Authority-Analysis: v=2.4 cv=JL0LdcKb c=1 sm=1 tr=0 ts=6a8c0de8 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=NH3m5DBF-mqJd7-nbgUA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwODI0MDA4MiBTYWx0ZWRfX2hD94qN7OBp4 7loP4CiDwxbj99v26IT7G8z21ix9yN1VLgHRZkZdzGXSjxG3LWaepPybx6a33xD4iUAUzpiFsV2 6XQq7ovPfwTR7mvbc4A08sua/rg9jwM= X-Proofpoint-GUID: 7uvxS_jII8HosrZTsmNk3P2nApPyCKKE X-Proofpoint-ORIG-GUID: 7uvxS_jII8HosrZTsmNk3P2nApPyCKKE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-24_03,2026-08-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 suspectscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 adultscore=0 bulkscore=0 malwarescore=0 spamscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608240082 On 8/12/26 10:30 AM, Kathiravan Thirumoorthy wrote: > On IPQ5424, the I2C controller can operate on both RTL-hardened SEs > and firmware-based SEs. As documented in commit 506bb2ab0075 > ("i2c: qcom-geni: Support systems with 32MHz serial engine clock"), > in IPQ5424 SEs use a 32 MHz source clock. > > The existing frequency table does not provide the required SCL timing > parameters for firmware-based SEs. Add a dedicated frequency table > using the SCL counter values recommended by the hardware design team > and select it for firmware-based SEs to achieve the target bus > frequencies. > > Move geni_i2c_clk_map_idx() from geni_i2c_resources_init() to > geni_i2c_init() to ensure SE_HW_PARAM_2 is accessed only after the > required clocks have been enabled. > > Signed-off-by: Kathiravan Thirumoorthy > --- > drivers/i2c/busses/i2c-qcom-geni.c | 25 ++++++++++++++++++------- > include/linux/soc/qcom/geni-se.h | 1 + > 2 files changed, 19 insertions(+), 7 deletions(-) > > diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c > index 00013b41a6f5..15835f10b062 100644 > --- a/drivers/i2c/busses/i2c-qcom-geni.c > +++ b/drivers/i2c/busses/i2c-qcom-geni.c > @@ -187,19 +187,28 @@ static const struct geni_i2c_clk_fld geni_i2c_clk_map_19p2mhz[] = { > }; > > /* source_clock = 32 MHz */ > -static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz[] = { > +static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz_minicore[] = { > { I2C_MAX_STANDARD_MODE_FREQ, 12, 9, 10, 26 }, > { I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 19 }, > { I2C_MAX_FAST_MODE_PLUS_FREQ, 2, 3, 5, 15 }, > {} > }; > > +static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz_fwcore[] = { > + { I2C_MAX_STANDARD_MODE_FREQ, 12, 9, 10, 25 }, > + { I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 18 }, > + { I2C_MAX_FAST_MODE_PLUS_FREQ, 1, 6, 15, 29 }, > + {} > +}; The fwcore one seems to be slightly "stricter" - wouldn't it work for both of them? Konrad