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[89.77.68.124]) by smtp.gmail.com with ESMTPSA id t17sm220669ljk.101.2021.11.02.03.05.57 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 02 Nov 2021 03:05:58 -0700 (PDT) Message-ID: <30b190ec-ec71-6b13-12cc-2822b1032d80@canonical.com> Date: Tue, 2 Nov 2021 11:05:57 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.1.2 Subject: Re: [PATCH v2 08/12] watchdog: s3c2410: Add support for WDT counter enable register Content-Language: en-US To: Sam Protsenko , Wim Van Sebroeck , Guenter Roeck , Rob Herring Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org References: <20211031122216.30212-1-semen.protsenko@linaro.org> <20211031122216.30212-9-semen.protsenko@linaro.org> From: Krzysztof Kozlowski In-Reply-To: <20211031122216.30212-9-semen.protsenko@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 31/10/2021 13:22, Sam Protsenko wrote: > On new Exynos chips (e.g. Exynos850) new CLUSTERx_NONCPU_OUT register is > introduced, where CNT_EN_WDT bit must be enabled to make watchdog > counter running. Add corresponding quirk and proper infrastructure to > handle that register if the quirk is set. > > This commit doesn't bring any functional change to existing devices, but > merely provides an infrastructure for upcoming chips support. > > Signed-off-by: Sam Protsenko > --- > Changes in v2: > - Used quirks instead of callbacks for all added PMU registers > - Used BIT() macro > - Extracted cleanup code to separate patch to minimize changes and > ease the review and porting > > drivers/watchdog/s3c2410_wdt.c | 28 +++++++++++++++++++++++++++- > 1 file changed, 27 insertions(+), 1 deletion(-) > Reviewed-by: Krzysztof Kozlowski Best regards, Krzysztof