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Fri, 17 Mar 2023 05:19:51 -0700 (PDT) Received: from [192.168.1.211] ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id v2-20020ac25602000000b004a0589786ddsm344236lfd.69.2023.03.17.05.19.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Mar 2023 05:19:51 -0700 (PDT) Message-ID: <30b349bd-c083-ed17-1e20-c84e4b67d449@linaro.org> Date: Fri, 17 Mar 2023 14:19:50 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v5 5/5] arm64: dts: qcom: sm8450: add dp controller Content-Language: en-GB To: Neil Armstrong , Rob Clark , Abhinav Kumar , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Kuogee Hsieh , Andy Gross , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230206-topic-sm8450-upstream-dp-controller-v5-0-a27f1b26ebe8@linaro.org> <20230206-topic-sm8450-upstream-dp-controller-v5-5-a27f1b26ebe8@linaro.org> From: Dmitry Baryshkov In-Reply-To: <20230206-topic-sm8450-upstream-dp-controller-v5-5-a27f1b26ebe8@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 17/03/2023 11:12, Neil Armstrong wrote: > Add the Display Port controller subnode to the MDSS node. > > Reviewed-by: Konrad Dybcio > Signed-off-by: Neil Armstrong > --- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 79 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 79 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 0b5a151ce138..41f5015e615b 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -2751,6 +2751,13 @@ dpu_intf2_out: endpoint { > }; > }; > > + port@2 { > + reg = <2>; > + dpu_intf0_out: endpoint { > + remote-endpoint = <&mdss_dp0_in>; > + }; > + }; > + > }; > > mdp_opp_table: opp-table { > @@ -2783,6 +2790,78 @@ opp-500000000 { > }; > }; > > + mdss_dp0: displayport-controller@ae90000 { > + compatible = "qcom,sm8450-dp", "qcom,sm8350-dp"; > + reg = <0 0xae90000 0 0x200>, > + <0 0xae90200 0 0x200>, > + <0 0xae90400 0 0xc00>, > + <0 0xae91000 0 0x400>, > + <0 0xae91400 0 0x400>; > + interrupt-parent = <&mdss>; > + interrupts = <12>; > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; > + clock-names = "core_iface", > + "core_aux", > + "ctrl_link", > + "ctrl_link_iface", > + "stream_pixel"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, > + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; > + assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, > + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; > + > + phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; > + phy-names = "dp"; > + > + #sound-dai-cells = <0>; > + > + operating-points-v2 = <&dp_opp_table>; > + power-domains = <&rpmhpd SM8450_MMCX>; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + mdss_dp0_in: endpoint { > + remote-endpoint = <&dpu_intf0_out>; > + }; > + }; > + }; > + > + dp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-19200000 { > + opp-hz = /bits/ 64 <19200000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; Yes, the vendor kernel has 19.2 MHz as a frequency for the low_svs. However I don't think we should do it this way, we list DP rates here, so the lowest entry should be RBR, 160000000. > + > + opp-270000000 { > + opp-hz = /bits/ 64 <270000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-540000000 { > + opp-hz = /bits/ 64 <540000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-810000000 { > + opp-hz = /bits/ 64 <810000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > + > mdss_dsi0: dsi@ae94000 { > compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; > reg = <0 0x0ae94000 0 0x400>; > -- With best wishes Dmitry