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[83.9.1.117]) by smtp.gmail.com with ESMTPSA id q17-20020a50c351000000b004aacd6b88ccsm2016167edb.90.2023.02.10.03.00.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 10 Feb 2023 03:00:54 -0800 (PST) Message-ID: <30c8c24b-4ae1-2623-a547-6dcb16b3974b@linaro.org> Date: Fri, 10 Feb 2023 12:00:52 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [PATCH v2 2/5] arm64: dts: qcom: sm8350: switch to combo usb3/dp phy To: Neil Armstrong , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Kuogee Hsieh , Andy Gross , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230206-topic-sm8450-upstream-dp-controller-v2-0-529da2203659@linaro.org> <20230206-topic-sm8450-upstream-dp-controller-v2-2-529da2203659@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20230206-topic-sm8450-upstream-dp-controller-v2-2-529da2203659@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10.02.2023 11:34, Neil Armstrong wrote: > The first QMP PHY is an USB3/DP combo phy, switch to the newly > documented bindings and register the clocks to the GCC > and DISPCC controllers. > > Signed-off-by: Neil Armstrong > --- > arch/arm64/boot/dts/qcom/sm8350.dtsi | 40 ++++++++++++------------------------ > 1 file changed, 13 insertions(+), 27 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > index 04bb838189a6..d490ce84a022 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > @@ -652,7 +652,7 @@ gcc: clock-controller@100000 { > <&ufs_mem_phy_lanes 0>, > <&ufs_mem_phy_lanes 1>, > <&ufs_mem_phy_lanes 2>, > - <0>, > + <&usb_1_qmpphy 0>, Please use the defines from include/dt-bindings/phy/phy-qcom-qmp.h > <0>; > }; > > @@ -2601,37 +2601,24 @@ usb_2_hsphy: phy@88e4000 { > resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; > }; > > - usb_1_qmpphy: phy-wrapper@88e9000 { > - compatible = "qcom,sm8350-qmp-usb3-phy"; > - reg = <0 0x088e9000 0 0x200>, > - <0 0x088e8000 0 0x20>; > - status = "disabled"; > - #address-cells = <2>; > - #size-cells = <2>; > - ranges; > + usb_1_qmpphy: phy@88e9000 { > + compatible = "qcom,sm8350-qmp-usb3-dp-phy"; > + reg = <0 0x088e8000 0 0x3000>; > > clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, > <&rpmhcc RPMH_CXO_CLK>, > - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; > - clock-names = "aux", "ref_clk_src", "com_aux"; > + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, > + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; > + clock-names = "aux", "ref", "com_aux", "usb3_pipe"; > > resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, > <&gcc GCC_USB3_PHY_PRIM_BCR>; > reset-names = "phy", "common"; > > - usb_1_ssphy: phy@88e9200 { > - reg = <0 0x088e9200 0 0x200>, > - <0 0x088e9400 0 0x200>, > - <0 0x088e9c00 0 0x400>, > - <0 0x088e9600 0 0x200>, > - <0 0x088e9800 0 0x200>, > - <0 0x088e9a00 0 0x100>; > - #phy-cells = <0>; > - #clock-cells = <0>; > - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; > - clock-names = "pipe0"; > - clock-output-names = "usb3_phy_pipe_clk_src"; > - }; > + #clock-cells = <1>; > + #phy-cells = <1>; > + > + status = "disabled"; > }; > > usb_2_qmpphy: phy-wrapper@88eb000 { > @@ -2727,7 +2714,7 @@ usb_1_dwc3: usb@a600000 { > iommus = <&apps_smmu 0x0 0x0>; > snps,dis_u2_susphy_quirk; > snps,dis_enblslpm_quirk; > - phys = <&usb_1_hsphy>, <&usb_1_ssphy>; > + phys = <&usb_1_hsphy>, <&usb_1_qmpphy 0>; And here too. Otherwise LGTM! Konrad > phy-names = "usb2-phy", "usb3-phy"; > }; > }; > @@ -3092,8 +3079,7 @@ dispcc: clock-controller@af00000 { > clocks = <&rpmhcc RPMH_CXO_CLK>, > <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, > <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, > - <0>, > - <0>; > + <&usb_1_qmpphy 1>, <&usb_1_qmpphy 2>; > clock-names = "bi_tcxo", > "dsi0_phy_pll_out_byteclk", > "dsi0_phy_pll_out_dsiclk", >