From: Jie Gan <jie.gan@oss.qualcomm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@linaro.org>,
James Clark <james.clark@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Tingwei Zhang <tingwei.zhang@oss.qualcomm.com>,
Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>,
Mao Jinlong <jinlong.mao@oss.qualcomm.com>,
Jie Gan <quic_jiegan@quicinc.com>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>
Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Subject: Re: [PATCH v7 0/9] coresight: ctcu: Enable byte-cntr function for TMC ETR
Date: Mon, 10 Nov 2025 10:42:13 +0800 [thread overview]
Message-ID: <30cc9d63-72a2-4dbd-89c5-d3a84e5a36de@oss.qualcomm.com> (raw)
In-Reply-To: <20251013-enable-byte-cntr-for-ctcu-v7-0-e1e8f41e15dd@oss.qualcomm.com>
On 10/13/2025 1:49 PM, Jie Gan wrote:
> The byte-cntr function provided by the CTCU device is used to count the
> trace data entering the ETR. An interrupt is triggered if the data size
> exceeds the threshold set in the BYTECNTRVAL register. The interrupt
> handler counts the number of triggered interruptions.
>
<...>
> Enable both ETR0 and ETR1:
> echo 0x10000 0x10000 > /sys/bus/coresight/devices/ctcu0/irq_threshold
>
> Reset the BYTECNTR register for etr0:
> echo 0 > /sys/bus/coresight/devices/ctcu0/irq_threshold
>
Gentle reminder.
> Changes in V7:
> 1. rebased on tag next-20251010
> 2. updated info for sysfs node document
> Link to V6 - https://lore.kernel.org/all/20250908-enable-byte-cntr-for-tmc-v6-0-1db9e621441a@oss.qualcomm.com/
>
<...>
next prev parent reply other threads:[~2025-11-10 2:42 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-13 5:49 Jie Gan
2025-10-13 5:49 ` [PATCH v7 1/9] coresight: core: Refactoring ctcu_get_active_port and make it generic Jie Gan
2025-10-13 5:49 ` [PATCH v7 2/9] coresight: core: add a new API to retrieve the helper device Jie Gan
2025-10-13 5:49 ` [PATCH v7 3/9] coresight: tmc: add etr_buf_list to store allocated etr_buf Jie Gan
2025-10-13 5:49 ` [PATCH v7 4/9] coresight: tmc: add create/clean functions for etr_buf_list Jie Gan
2025-10-13 5:49 ` [PATCH v7 5/9] coresight: tmc: Introduce sysfs_read_ops to wrap sysfs read operations Jie Gan
2025-10-13 5:49 ` [PATCH v7 6/9] dt-bindings: arm: add an interrupt property for Coresight CTCU Jie Gan
2025-10-13 5:49 ` [PATCH v7 7/9] coresight: ctcu: enable byte-cntr for TMC ETR devices Jie Gan
2025-10-13 5:49 ` [PATCH v7 8/9] coresight: tmc: integrate byte-cntr's read_ops with sysfs file_ops Jie Gan
2025-10-13 5:49 ` [PATCH v7 9/9] arm64: dts: qcom: lemans: Add interrupts to CTCU device Jie Gan
2025-10-27 1:12 ` [PATCH v7 0/9] coresight: ctcu: Enable byte-cntr function for TMC ETR Jie Gan
2025-11-10 2:42 ` Jie Gan [this message]
2025-12-03 12:29 ` Jie Gan
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