From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51F2E2C2374 for ; Tue, 16 Dec 2025 09:39:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765877945; cv=none; b=qZLT05PnjdY9ee8/Xm7tR8DwZj3Tr/AwfP85Mr44Q4JKpYg53blzhK8Wtm1KtETadraL3fgBRdiJPFGAXlpE4OAhhjCyBBBP1btNNQWWXDS0guSyhLL2OgBNbuTxupCGcVYFEKlpKm+EQutD//Gq6q0nGFE3xJIOaqvc2gi9L1A= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765877945; c=relaxed/simple; bh=q1Hcf1k/kvvCx6xLg+3dCNq6247Sbheq11HzrNtB3OY=; h=Message-ID:Date:MIME-Version:Subject:To:References:From: In-Reply-To:Content-Type; b=HqtvnHQKi7LXPExCABY3zK5HhFMiIJ9fis+2U8MVsX35lNAr8xI8tMmLrzR4yRxI2i3MFnrTns8nr7zxf8/ADo8u+kOsSJjj5epP8uNwIsCPYKRxz0mCCRLm+EfPGR6+Iur1hK0jGcqpmZ9BxoPoNW5m2HWOZwwg7tLK9LEUga8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nEEOZ8Qs; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nEEOZ8Qs" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 25660C4CEF1; Tue, 16 Dec 2025 09:38:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1765877944; bh=q1Hcf1k/kvvCx6xLg+3dCNq6247Sbheq11HzrNtB3OY=; h=Date:Subject:To:References:From:In-Reply-To:From; b=nEEOZ8QslSTo4sx9NG7KR57gpJdugpII2VRi54oudi+rSrJf2dsrIWbvBwPvAMFEr 5a+chhEa8U0S+KX1UsUlftFQsw1lazn9DnNH7/Gb1w3K/hdnAlTWy7eeAd3d1NVLvt 5uSXL4hka0mSB2HvQJYKP3gpwY9jXy8gmh4tDBrVqQb/Z51J+RYR98wGZqFaSGJADh c9BjOeH7Lpd81c701iYUvQ8JfopcC8gveFktOKLyaZv9lwtYQV+jYKOQP0tpAX8XeD BOcsy4LwgYM+2FRy04ZPb74kFfamLXwY0h0ZZ+E4Q3AbwRVrM0Bcy4LWU9ewYjcF0q 5/VIzmxjDv7Hg== Message-ID: <30d26b5c-7a5d-403e-a10b-381d09cae3b9@kernel.org> Date: Tue, 16 Dec 2025 10:38:50 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/8] powerpc: introduce arch_enter_from_user_mode To: Mukesh Kumar Chaurasiya , maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, oleg@redhat.com, kees@kernel.org, luto@amacapital.net, wad@chromium.org, mchauras@linux.ibm.com, thuth@redhat.com, sshegde@linux.ibm.com, charlie@rivosinc.com, macro@orcam.me.uk, akpm@linux-foundation.org, ldv@strace.io, deller@gmx.de, ankur.a.arora@oracle.com, segher@kernel.crashing.org, tglx@linutronix.de, thomas.weissschuh@linutronix.de, peterz@infradead.org, menglong8.dong@gmail.com, bigeasy@linutronix.de, namcao@linutronix.de, kan.liang@linux.intel.com, mingo@kernel.org, atrajeev@linux.vnet.ibm.com, mark.barnett@arm.com, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org References: <20251214130245.43664-1-mkchauras@linux.ibm.com> <20251214130245.43664-4-mkchauras@linux.ibm.com> Content-Language: fr-FR From: "Christophe Leroy (CS GROUP)" In-Reply-To: <20251214130245.43664-4-mkchauras@linux.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Le 14/12/2025 à 14:02, Mukesh Kumar Chaurasiya a écrit : > From: Mukesh Kumar Chaurasiya > > Implement the arch_enter_from_user_mode() hook required by the generic > entry/exit framework. This helper prepares the CPU state when entering > the kernel from userspace, ensuring correct handling of KUAP/KUEP, > transactional memory, and debug register state. > > As part of this change, move booke_load_dbcr0() from interrupt.c to > interrupt.h so it can be used by the new helper without introducing > cross-file dependencies. > > This patch contains no functional changes, it is purely preparatory for > enabling the generic syscall and interrupt entry path on PowerPC. > > Signed-off-by: Mukesh Kumar Chaurasiya > --- > arch/powerpc/include/asm/entry-common.h | 97 +++++++++++++++++++++++++ > arch/powerpc/include/asm/interrupt.h | 22 ++++++ > arch/powerpc/kernel/interrupt.c | 22 ------ > 3 files changed, 119 insertions(+), 22 deletions(-) > > diff --git a/arch/powerpc/include/asm/entry-common.h b/arch/powerpc/include/asm/entry-common.h > index 3af16d821d07..093ece06ef79 100644 > --- a/arch/powerpc/include/asm/entry-common.h > +++ b/arch/powerpc/include/asm/entry-common.h > @@ -5,7 +5,104 @@ > > #ifdef CONFIG_GENERIC_IRQ_ENTRY This #ifdef is still unnecessary it seems. > > +#include > +#include > #include > +#include > + > +static __always_inline void arch_enter_from_user_mode(struct pt_regs *regs) > +{ > + if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) > + BUG_ON(irq_soft_mask_return() != IRQS_ALL_DISABLED); > + > + BUG_ON(regs_is_unrecoverable(regs)); > + BUG_ON(!user_mode(regs)); > + BUG_ON(regs_irqs_disabled(regs)); > + > +#ifdef CONFIG_PPC_PKEY > + if (mmu_has_feature(MMU_FTR_PKEY) && trap_is_syscall(regs)) { > + unsigned long amr, iamr; > + bool flush_needed = false; > + /* > + * When entering from userspace we mostly have the AMR/IAMR > + * different from kernel default values. Hence don't compare. > + */ > + amr = mfspr(SPRN_AMR); > + iamr = mfspr(SPRN_IAMR); > + regs->amr = amr; > + regs->iamr = iamr; > + if (mmu_has_feature(MMU_FTR_KUAP)) { > + mtspr(SPRN_AMR, AMR_KUAP_BLOCKED); > + flush_needed = true; > + } > + if (mmu_has_feature(MMU_FTR_BOOK3S_KUEP)) { > + mtspr(SPRN_IAMR, AMR_KUEP_BLOCKED); > + flush_needed = true; > + } > + if (flush_needed) > + isync(); > + } else > +#endif > + kuap_assert_locked(); This construct is odd, can you do something about it ? > + > + booke_restore_dbcr0(); > + > + account_cpu_user_entry(); > + > + account_stolen_time(); > + > + /* > + * This is not required for the syscall exit path, but makes the > + * stack frame look nicer. If this was initialised in the first stack > + * frame, or if the unwinder was taught the first stack frame always > + * returns to user with IRQS_ENABLED, this store could be avoided! > + */ > + irq_soft_mask_regs_set_state(regs, IRQS_ENABLED); > + > + /* > + * If system call is called with TM active, set _TIF_RESTOREALL to > + * prevent RFSCV being used to return to userspace, because POWER9 > + * TM implementation has problems with this instruction returning to > + * transactional state. Final register values are not relevant because > + * the transaction will be aborted upon return anyway. Or in the case > + * of unsupported_scv SIGILL fault, the return state does not much > + * matter because it's an edge case. > + */ > + if (IS_ENABLED(CONFIG_PPC_TRANSACTIONAL_MEM) && > + unlikely(MSR_TM_TRANSACTIONAL(regs->msr))) > + set_bits(_TIF_RESTOREALL, ¤t_thread_info()->flags); > + > + /* > + * If the system call was made with a transaction active, doom it and > + * return without performing the system call. Unless it was an > + * unsupported scv vector, in which case it's treated like an illegal > + * instruction. > + */ > +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM > + if (unlikely(MSR_TM_TRANSACTIONAL(regs->msr)) && > + !trap_is_unsupported_scv(regs)) { > + /* Enable TM in the kernel, and disable EE (for scv) */ > + hard_irq_disable(); > + mtmsr(mfmsr() | MSR_TM); > + > + /* tabort, this dooms the transaction, nothing else */ > + asm volatile(".long 0x7c00071d | ((%0) << 16)" > + :: "r"(TM_CAUSE_SYSCALL | TM_CAUSE_PERSISTENT)); > + > + /* > + * Userspace will never see the return value. Execution will > + * resume after the tbegin. of the aborted transaction with the > + * checkpointed register state. A context switch could occur > + * or signal delivered to the process before resuming the > + * doomed transaction context, but that should all be handled > + * as expected. > + */ > + return; > + } > +#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ > +} > + > +#define arch_enter_from_user_mode arch_enter_from_user_mode > > #endif /* CONFIG_GENERIC_IRQ_ENTRY */ > #endif /* _ASM_PPC_ENTRY_COMMON_H */ > diff --git a/arch/powerpc/include/asm/interrupt.h b/arch/powerpc/include/asm/interrupt.h > index 0e2cddf8bd21..ca8a2cda9400 100644 > --- a/arch/powerpc/include/asm/interrupt.h > +++ b/arch/powerpc/include/asm/interrupt.h > @@ -138,6 +138,28 @@ static inline void nap_adjust_return(struct pt_regs *regs) > #endif > } > > +static inline void booke_load_dbcr0(void) It was a notrace function in interrupt.c Should it be an __always_inline now ? Christophe > +{ > +#ifdef CONFIG_PPC_ADV_DEBUG_REGS > + unsigned long dbcr0 = current->thread.debug.dbcr0; > + > + if (likely(!(dbcr0 & DBCR0_IDM))) > + return; > + > + /* > + * Check to see if the dbcr0 register is set up to debug. > + * Use the internal debug mode bit to do this. > + */ > + mtmsr(mfmsr() & ~MSR_DE); > + if (IS_ENABLED(CONFIG_PPC32)) { > + isync(); > + global_dbcr0[smp_processor_id()] = mfspr(SPRN_DBCR0); > + } > + mtspr(SPRN_DBCR0, dbcr0); > + mtspr(SPRN_DBSR, -1); > +#endif > +} > + > static inline void booke_restore_dbcr0(void) > { > #ifdef CONFIG_PPC_ADV_DEBUG_REGS > diff --git a/arch/powerpc/kernel/interrupt.c b/arch/powerpc/kernel/interrupt.c > index 0d8fd47049a1..2a09ac5dabd6 100644 > --- a/arch/powerpc/kernel/interrupt.c > +++ b/arch/powerpc/kernel/interrupt.c > @@ -78,28 +78,6 @@ static notrace __always_inline bool prep_irq_for_enabled_exit(bool restartable) > return true; > } > > -static notrace void booke_load_dbcr0(void) > -{ > -#ifdef CONFIG_PPC_ADV_DEBUG_REGS > - unsigned long dbcr0 = current->thread.debug.dbcr0; > - > - if (likely(!(dbcr0 & DBCR0_IDM))) > - return; > - > - /* > - * Check to see if the dbcr0 register is set up to debug. > - * Use the internal debug mode bit to do this. > - */ > - mtmsr(mfmsr() & ~MSR_DE); > - if (IS_ENABLED(CONFIG_PPC32)) { > - isync(); > - global_dbcr0[smp_processor_id()] = mfspr(SPRN_DBCR0); > - } > - mtspr(SPRN_DBCR0, dbcr0); > - mtspr(SPRN_DBSR, -1); > -#endif > -} > - > static notrace void check_return_regs_valid(struct pt_regs *regs) > { > #ifdef CONFIG_PPC_BOOK3S_64