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([2a02:810d:15c0:828:a3bf:4ed:6c53:2a36]) by smtp.gmail.com with ESMTPSA id wt10-20020a170906ee8a00b0094f225c0cd3sm421385ejb.86.2023.04.15.02.00.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 15 Apr 2023 02:00:50 -0700 (PDT) Message-ID: <310e8979-de96-dda8-6c95-0e6033d8b403@linaro.org> Date: Sat, 15 Apr 2023 11:00:49 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH 7/7] ASoC: dt-bindings: mediatek,mt8188-afe: add audio properties Content-Language: en-US To: Trevor Wu , broonie@kernel.org, lgirdwood@gmail.com, tiwai@suse.com, perex@perex.cz, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com Cc: alsa-devel@alsa-project.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20230413104713.7174-1-trevor.wu@mediatek.com> <20230413104713.7174-8-trevor.wu@mediatek.com> From: Krzysztof Kozlowski In-Reply-To: <20230413104713.7174-8-trevor.wu@mediatek.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 13/04/2023 12:47, Trevor Wu wrote: > Assign top_a1sys_hp clock to 26M, and add apll1_d4 to clocks for switching > the parent of top_a1sys_hp dynamically > On the other hand, "mediatek,infracfg" is included for bus protection. > > Signed-off-by: Trevor Wu > --- > .../bindings/sound/mediatek,mt8188-afe.yaml | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml > index 82ccb32f08f2..03301d5082f3 100644 > --- a/Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml > +++ b/Documentation/devicetree/bindings/sound/mediatek,mt8188-afe.yaml > @@ -29,6 +29,10 @@ properties: > $ref: /schemas/types.yaml#/definitions/phandle > description: The phandle of the mediatek topckgen controller > > + mediatek,infracfg: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: The phandle of the mediatek infracfg controller > + > power-domains: > maxItems: 1 > > @@ -37,6 +41,7 @@ properties: > - description: 26M clock > - description: audio pll1 clock > - description: audio pll2 clock > + - description: audio pll1 divide 4 > - description: clock divider for i2si1_mck > - description: clock divider for i2si2_mck > - description: clock divider for i2so1_mck > @@ -58,6 +63,7 @@ properties: > - const: clk26m > - const: apll1 > - const: apll2 > + - const: apll1_d4 Why do you add clocks in the middle? The order is strict, so you just broke all DTS. > - const: apll12_div0 > - const: apll12_div1 > - const: apll12_div2 > @@ -74,6 +80,12 @@ properties: > - const: i2si2_m_sel > - const: adsp_audio_26m > > + assigned-clocks: > + maxItems: 1 > + > + assigned-clock-parents: > + maxItems: 1 Usually these two are not needed. > + > mediatek,etdm-in1-cowork-source: > $ref: /schemas/types.yaml#/definitions/uint32 > description: > @@ -147,6 +159,8 @@ required: > - power-domains > - clocks > - clock-names > + - assigned-clocks > + - assigned-clock-parents Why making them required? Best regards, Krzysztof